SMECY envisions that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments, which
due to improved performance, energy and cost properties will, in a few years, extensively penetrate the embedded system industry sectors.
This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core
platforms to diverse application sectors, Intellectual Property (IP) providers need to re-target existing and develop new solutions to be
compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and
renewing their system, architecture, software and hardware development processes.
The complexity of future smart multi-core embedded systems requires holistic system integration because of stringent constraints on e.g.
performance and time to market that can only be mastered using a design approach that optimizes interaction between SoC design and
Embedded Software approaches. Therefore, many companies that traditionally have a culture rooted in nano and microelectronics express an
urgent need in acquiring know-how and competences in embedded software. Equally urgent is the need of embedded system houses to be
able to transform their current product assets to use multi-cores and at the same time to establish development processes in order to fully
exploit them.
The mission of the SMECY project is to develop new programming technologies enabling the exploitation of many (100s) core architectures.
Multi-core technologies are strategic to keep and win market shares in all areas of embedded systems. ARTEMIS covers well most aspects of
embedded systems, but efficient programming of multi-core architectures for various resources-constrained embedded system applications,
such as consumer, wireless and some transportation fields, is still a grand challenge waiting to be solved. The goal of this ARTEMIS project is
to launch an ambitious European initiative to allow Europe to catch up with Asia (e.g. teams funded by JST/CREST programmes) and USA
(e.g. PARLAB in Berkeley, Parallel@illinois and Pervasive Parallelism Laboratory in Stanford) and to enable Europe to become the leader.
The key outcomes of the SMECY project are programming and design methods, multi-core programmable architectural solutions and
associated supporting tools that enable a holistic integration of multi-core SoC design and embedded software to master smart system design
of future smart multi-core embedded systems in different applications, e.g. consumer, wireless, communication and transportation.

Popis česky
SMECY envisions that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments, which
due to improved performance, energy and cost properties will, in a few years, extensively penetrate the embedded system industry sectors.
This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core
platforms to diverse application sectors, Intellectual Property (IP) providers need to re-target existing and develop new solutions to be
compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and
renewing their system, architecture, software and hardware development processes.
The complexity of future smart multi-core embedded systems requires holistic system integration because of stringent constraints on e.g.
performance and time to market that can only be mastered using a design approach that optimizes interaction between SoC design and
Embedded Software approaches. Therefore, many companies that traditionally have a culture rooted in nano and microelectronics express an
urgent need in acquiring know-how and competences in embedded software. Equally urgent is the need of embedded system houses to be
able to transform their current product assets to use multi-cores and at the same time to establish development processes in order to fully
exploit them.
The mission of the SMECY project is to develop new programming technologies enabling the exploitation of many (100s) core architectures.
Multi-core technologies are strategic to keep and win market shares in all areas of embedded systems. ARTEMIS covers well most aspects of
embedded systems, but efficient programming of multi-core architectures for various resources-constrained embedded system applications,
such as consumer, wireless and some transportation fields, is still a grand challenge waiting to be solved. The goal of this ARTEMIS project is
to launch an ambitious European initiative to allow Europe to catch up with Asia (e.g. teams funded by JST/CREST programmes) and USA
(e.g. PARLAB in Berkeley, Parallel@illinois and Pervasive Parallelism Laboratory in Stanford) and to enable Europe to become the leader.
The key outcomes of the SMECY project are programming and design methods, multi-core programmable architectural solutions and
associated supporting tools that enable a holistic integration of multi-core SoC design and embedded software to master smart system design
of future smart multi-core embedded systems in different applications, e.g. consumer, wireless, communication and transportation.

Klíčová slova
multi-core architectures, embedded systems

7H10014

angličtina

Zemčík Pavel, prof. Dr. Ing., dr. h. c. - hlavní řešitel

Ústav počítačové grafiky a multimédií
- odpovědné pracoviště (6.4.2010 - nezadáno)

JURÁNKOVÁ, M.; HEROUT, A.; ZEMČÍK, P.: Multiplatform Software for Line Detection. URL: http://www.fit.vutbr.cz/research/prod/index.php?id=213. (Software)
Detail

BAŘINA, D.; ZEMČÍK, P.: A Cross-platform Discrete Wavelet Transform Library 2. URL: http://www.fit.vutbr.cz/research/view_product.php.cs?id=282¬itle=1. (Software)
Detail

BAŘINA, D.; JURÁNEK, R.; JURÁNKOVÁ, M.; NEČAS, O.; ZEMČÍK, P.: Set of image processing algorithms resulting from SMECY. URL: http://www.fit.vutbr.cz/units/UPGM/prod/index.php?id=284¬itle=1www.smecy.eu. (Software)
Detail

NEČAS, O.; HEROUT, A.; ZEMČÍK, P.; BAŘINA, D.: Hierarchy of Parts. URL: http://www.fit.vutbr.cz/research/view_product.php.cs?id=167. (Software)
Detail

HUSÁR, A.; HRUŠKA, T.; MASAŘÍK, K.: RAVAC. URL: http://www.fit.vutbr.cz/research/prod/index.php?id=266. (Software)
Detail

JURÁNEK, R.; ZEMČÍK, P.; HRADIŠ, M.; HEROUT, A.: Multiplatform Framework for Object Detection. URL: http://www.fit.vutbr.cz/research/prod/index.php?id=212. (Software)
Detail

BAŘINA, D.; ZEMČÍK, P.: A Cross-platform Discrete Wavelet Transform Library. URL: http://www.fit.vutbr.cz/research/view_product.php.cs?id=211¬itle=1. (Software)
Detail

ĎURFINA, L.; KŘOUSTEK, J.; ZEMEK, P.; KOLÁŘ, D.; HRUŠKA, T.; MASAŘÍK, K.; MEDUNA, A. Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis. The 5th International Conference on Information Security and Assurance. Communications in Computer and Information Science, Volume 200. Brno: Springer Verlag, 2011. p. 72.ISBN: 978-3-642-23140-7.
Detail

BAŘINA, D. Gabor Wavelets in Image Processing. Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Brno University of Technology, 2011. p. 522.ISBN: 978-80-214-4273-3.
Detail

JURÁNEK, R.; HRADIŠ, M.; ZEMČÍK, P. Real-time Algorithms of Object Detection using Classifiers. In Real-Time System. Rijeka: InTech - Open Access Publisher, 2012. p. 1.ISBN: 9789535105107.
Detail

DOLÍHAL, L.; HRUŠKA, T.; MASAŘÍK, K. Usage of simulators in testing system. Industrial Simulation Conference. Brno: EUROSIS, 2012. p. 74.ISBN: 978-90-77381-71-7.
Detail

PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Just-In-Time Translated Simulation for ASIP Design. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011. p. 279-282. ISBN: 978-1-4244-9753-9.
Detail

DOLÍHAL, L.; HRUŠKA, T.; MASAŘÍK, K. Testing of an automatically generated compiler, Review of retargetable testing system. International Journal on Advances in Software, 2012, vol. 2012, iss. 1, p. 15-26. ISSN: 1942-2628.
Detail

ŘEZNÍČEK, I.; BAŘINA, D. Classifier creation framework for diverse classification tasks. Proceedings of the DT workshop. Žilina: Brno University of Technology, 2010. p. 50.ISBN: 978-80-554-0304-5.
Detail

JURÁNKOVÁ, M.; HEROUT, A.; HAVEL, J. PClines - Line Detection Using Parallel Coordinates. Proceedings of CVPR 2011. Colorado Springs: IEEE Computer Society, 2011. p. 1489.ISBN: 978-1-4577-0393-5.
Detail

ĎURFINA, L.; KŘOUSTEK, J.; ZEMEK, P.; KOLÁŘ, D.; HRUŠKA, T.; MASAŘÍK, K.; MEDUNA, A. Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis. International Journal of Security and Its Applications, 2011, vol. 5, iss. 4, p. 91-106. ISSN: 1738-9976.
Detail

JOŠTH, R.; JURÁNKOVÁ, M.; HEROUT, A.; HAVEL, J. Real-Time Line Detection Using Accelerated High-Resolution Hough Transform. Proceedings of SCIA 2011, LNCS. Ystad: Springer Verlag, 2011. p. 784.ISBN: 978-3-642-21226-0.
Detail

HAVEL, J.; JURÁNKOVÁ, M.; HEROUT, A.; JOŠTH, R. Real-Time Detection of Lines using Parallel Coordinates and CUDA. Journal of Real-Time Image Processing, 2014, vol. 2014, iss. 9, p. 205-216. ISSN: 1861-8200.
Detail

HRADIŠ, M.; BERAN, V.; ŘEZNÍČEK, I.; HEROUT, A.; BAŘINA, D.; VLČEK, A.; ZEMČÍK, P. Brno University of Technology at TRECVid 2010 SIN, CCD. In 2010 TREC Video Retrieval Evaluation Notebook Papers. Gaithersburg, MD: National Institute of Standards and Technology, 2010. p. 1-10.
Detail

JURÁNKOVÁ, M.; HEROUT, A.; HAVEL, J. Real-Time Precise Detection of Regular Grids and Matrix Codes. Journal of Real-Time Image Processing, 2016, vol. 11, iss. 1, p. 193-200. ISSN: 1861-8200.
Detail

NEČAS, O.; BAŘINA, D. Using Hierarchy of Parts for Image Classification. Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Brno University of Technology, 2011. p. 532.ISBN: 978-80-214-4273-3.
Detail

PŘIKRYL, Z.; MASAŘÍK, K.; HRUŠKA, T.; HUSÁR, A. Generated Cycle-Accurate Profiler for C Language. 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010. p. 263.ISBN: 978-0-7695-4171-6.
Detail

PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Translated Simulation of ASIPs. OpenAccess Series in Informatics (OASIcs), 2011, vol. 16, iss. 1, p. 93-100. ISSN: 2190-6807.
Detail

PŘIKRYL, Z.; HRUŠKA, T.; MASAŘÍK, K.; HUSÁR, A. Fast Cycle-Accurate Compiled Simulation. 10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010. Programmable devices and systems. Pszczyna: IFAC, 2010. iss. 10, p. 97.ISBN: 978-3-902661-95-1. ISSN: 1474-6670.
Detail

JURÁNEK, R. Acceleration of Object Detection Using Classifiers. Brno: Faculty of Information Technology BUT, 2012. p. 1.
Detail

HAVEL, J.; HEROUT, A.; JURÁNKOVÁ, M. Vanishing Points in Point-to-Line Mappings and Other Line Parameterizations. Pattern Recognition Letters, 2013, vol. 2013, iss. 34, p. 703-708. ISSN: 0167-8655.
Detail

PRISTACH, M.; HUSÁR, A.; FUJCIK, L.; HRUŠKA, T.; MASAŘÍK, K. Digital Signal Soft-Processor for Video Processing. In Electronic Devices and Systems IMAPS CS International Conference 2011 Proceedings. první. Brno: Vysoké učení technické v Brně, 2011. p. 180-185. ISBN: 978-80-214-4303-7.
Detail

JURÁNKOVÁ, M.; HAVEL, J.; HEROUT, A. Real-Time Detection of Lines using Parallel Coordinates and OpenGL. Proceedings of SCCG 2011. Bratislava: Comenius University in Bratislava, 2011. p. 1.ISBN: 978-80-223-3018-3.
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PŘIKRYL, Z. Advanced Methods of Microprocessor Simulation. Information Sciences and Technologies Bulletin of the ACM Slovakia, 2011, vol. 3, iss. 3, p. 1-13. ISSN: 1338-1237.
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PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Translated Simulation of ASIPs. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 135.ISBN: 978-80-87342-10-7.
Detail

PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D.; MASAŘÍK, K.; HUSÁR, A. Design and Simulation of High Performance Parallel Architectures Using the ISAC Language. GSTF International Journal on Computing, 2011, vol. 1, iss. 2, p. 97-106. ISSN: 2010-2283.
Detail

TRMAČ, M.; HUSÁR, A.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K. Instructor Selector Generation from Architecture Description. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 167.ISBN: 978-80-87342-10-7.
Detail

DOLÍHAL, L.; HRUŠKA, T. Porting of C library, Testing of generated compiler. InfoWare 2011. Luxembourg: International Academy, Research, and Industry Association, 2011. p. 125.ISBN: 978-1-61208-008-6.
Detail

KŘOUSTEK, J.; PŘIKRYL, Z.; KOLÁŘ, D.; HRUŠKA, T. Retargetable Multi-level Debugging in HW/SW Codesign. The 23rd International Conference on Microelectronics (ICM 2011). Hammamet: Institute of Electrical and Electronics Engineers, 2011. p. 1.ISBN: 978-1-4577-2209-7.
Detail

KŘOUSTEK, J.; ŽIDEK, S.; KOLÁŘ, D.; MEDUNA, A. Scattered Context Grammars with Priority. International Journal of Advanced Research in Computer Science, 2011, vol. 2, iss. 4, p. 1-6. ISSN: 0976-5697.
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HUSÁR, A.; TRMAČ, M.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K.; KOLÁŘ, D.; PŘIKRYL, Z. Automatic C Compiler Generation from Architecture Description Language ISAC. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 84.ISBN: 978-80-87342-10-7.
Detail

Odpovědnost: Zemčík Pavel, prof. Dr. Ing., dr. h. c.