Detail publikace

Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors

CHARVÁT, L. SMRČKA, A. VOJNAR, T.

Originální název

Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors

Typ

zpráva odborná

Jazyk

angličtina

Originální abstrakt

Implementation of a pipeline-based execution of instructions in purpose-specific microprocessors is an error prone task, which implies a need of proper verification of the resulting design. Various techniques were proposed for this purpose, but they usually require a significant manual intervention of the developers. In this work, we propose a novel, highly automated approach for discovering RAW hazards in in-order pipelined instruction execution. Our approach combines static analysis of data paths to detect anomalies and possible hazards, followed by a transformation of detected problematic paths to a parameterised system, and a subsequent formal verification to check the possibility of unhandled hazards using techniques for formal verification of parameterised systems. We have implemented our approach and successfully applied it on multiple non-trivial microprocessors.

Klíčová slova

automatic formal verification, microprocessor, register transfer level description, parameterised system, RAW hazard

Autoři

CHARVÁT, L.; SMRČKA, A.; VOJNAR, T.

Vydáno

22. 10. 2014

Nakladatel

Faculty of Information Technology BUT

Místo

Brno

Strany počet

18

URL

http://www.fit.vutbr.cz/research/groups/verifit/tools/hades/techrep/hades-techrep.pdf

BibTex

@techreport{BUT192973,
  author="Lukáš {Charvát} and Aleš {Smrčka} and Tomáš {Vojnar}",
  title="Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors",
  year="2014",
  publisher="Faculty of Information Technology BUT",
  address="Brno",
  pages="18",
  url="http://www.fit.vutbr.cz/research/groups/verifit/tools/hades/techrep/hades-techrep.pdf"
}