Detail publikačního výsledku

FPGA Based 1 Gbps Ethernet Header Detector

ŠTOHANZL, M.; POVALAČ, A.

Originální název

FPGA Based 1 Gbps Ethernet Header Detector

Anglický název

FPGA Based 1 Gbps Ethernet Header Detector

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

This paper presents a study about a hardware implementation of the Ethernet header detector implemented in FPGA circuits. The header detector is able to detect the TCP/IP and UDP/IP header contents for both the IPv4 and the IPv6 protocols. This hardware implementation allows access to the headers content faster than the software implementation. Therefore, it is suitable for many different high-speed Ethernet devices.

Anglický abstrakt

This paper presents a study about a hardware implementation of the Ethernet header detector implemented in FPGA circuits. The header detector is able to detect the TCP/IP and UDP/IP header contents for both the IPv4 and the IPv6 protocols. This hardware implementation allows access to the headers content faster than the software implementation. Therefore, it is suitable for many different high-speed Ethernet devices.

Klíčová slova

Field Programmable Gate Array (FPGA), Ethernet, header, IP, TCP, UDP

Klíčová slova v angličtině

Field Programmable Gate Array (FPGA), Ethernet, header, IP, TCP, UDP

Autoři

ŠTOHANZL, M.; POVALAČ, A.

Rok RIV

2013

Vydáno

29.08.2012

ISBN

978-80-214-4579-6

Kniha

Proceedings of the conference Vsacký Cáb 2012

Strany od

1

Strany do

4

Strany počet

4

BibTex

@inproceedings{BUT93622,
  author="Milan {Štohanzl} and Aleš {Povalač}",
  title="FPGA Based 1 Gbps Ethernet Header Detector",
  booktitle="Proceedings of the conference Vsacký Cáb 2012",
  year="2012",
  pages="1--4",
  isbn="978-80-214-4579-6"
}