Detail aplikovaného výsledku

HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware

ZACHARIÁŠOVÁ, M.; LENGÁL, O.; KAJAN, M.

Originální název

HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware

Anglický název

HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware

Druh

Software

Abstrakt

A framework compliant with current prevalent functional verification methodologies (OVM, UVM) that enables to accelerate functional verification of hardware components in an FPGA environment, thus significantly increasing performance of verification.

Abstrakt aglicky

A framework compliant with current prevalent functional verification methodologies (OVM, UVM) that enables to accelerate functional verification of hardware components in an FPGA environment, thus significantly increasing performance of verification.

Klíčová slova

functional verification, SystemVerilog, FPGA, acceleration, NetCOPE

Klíčová slova anglicky

functional verification, SystemVerilog, FPGA, acceleration, NetCOPE

Umístění

Nástroj i dokumentaci lze získat na URL http://www.fit.vutbr.cz/~isimkova/haven/ (http://www.fit.vutbr.cz/%7Eisimkova/haven/)

Licenční poplatek

K využití výsledku jiným subjektem je vždy nutné nabytí licence

www

https://www.fit.vut.cz/research/product/234/