Detail publikačního výsledku

High-level Modeling, Analysis and Verification of Programmable Hardware Design

SMRČKA, A.

Originální název

High-level Modeling, Analysis and Verification of Programmable Hardware Design

Anglický název

High-level Modeling, Analysis and Verification of Programmable Hardware Design

Druh

Abstrakt

Originální abstrakt

This work presents an abstract model of the design and verification ofseveral safety properties. The main task was to check if there is arisk of buffer overflow and how to set the length of buffers to preventthis. This work shows how to model such acomplex system by hand and particular results of analysis andverification is also presented.

Anglický abstrakt

This work presents an abstract model of the design and verification ofseveral safety properties. The main task was to check if there is arisk of buffer overflow and how to set the length of buffers to preventthis. This work shows how to model such acomplex system by hand and particular results of analysis andverification is also presented.

Klíčová slova

formal verification, high-level verification, hardware design analysis, throughput checking, timed analysis

Klíčová slova v angličtině

formal verification, high-level verification, hardware design analysis, throughput checking, timed analysis

Autoři

SMRČKA, A.

Vydáno

24.04.2006

Nakladatel

Technical University Wien

Místo

Vienna

ISBN

3-902463-05-8

Kniha

Proceedings of the Junior Scientist Conference 2006

Strany od

93

Strany do

94

Strany počet

3

BibTex

@misc{BUT60508,
  author="Aleš {Smrčka}",
  title="High-level Modeling, Analysis and Verification of Programmable Hardware Design",
  booktitle="Proceedings of the Junior Scientist Conference 2006",
  year="2006",
  pages="93--94",
  publisher="Technical University Wien",
  address="Vienna",
  isbn="3-902463-05-8",
  note="Abstract"
}