Detail publikačního výsledku

The Design of On-line Checkers and Their Use in Verification and Testing

KOTÁSEK, Z.; STRAKA, M.

Originální název

The Design of On-line Checkers and Their Use in Verification and Testing

Anglický název

The Design of On-line Checkers and Their Use in Verification and Testing

Druh

Článek recenzovaný mimo WoS a Scopus

Originální abstrakt

In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.

Anglický abstrakt

In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.

Klíčová slova

on-line checker, on-line testing, verification, communication protocol, PSL, FoCs, ModelSim, FPGA

Klíčová slova v angličtině

on-line checker, on-line testing, verification, communication protocol, PSL, FoCs, ModelSim, FPGA

Autoři

KOTÁSEK, Z.; STRAKA, M.

Rok RIV

2011

Vydáno

01.09.2009

ISSN

1335-8243

Periodikum

Acta Electrotechnica et Informatica

Svazek

2009

Číslo

3

Stát

Slovenská republika

Strany od

8

Strany do

15

Strany počet

8

BibTex

@article{BUT47975,
  author="Zdeněk {Kotásek} and Martin {Straka}",
  title="The Design of On-line Checkers and Their Use in Verification and Testing",
  journal="Acta Electrotechnica et Informatica",
  year="2009",
  volume="2009",
  number="3",
  pages="8--15",
  issn="1335-8243"
}