Detail publikačního výsledku

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.

Originální název

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

Anglický název

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Anglický abstrakt

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Klíčová slova

fault tolerant systems, reconfiguration, controller, FPGA, architecture

Klíčová slova v angličtině

fault tolerant systems, reconfiguration, controller, FPGA, architecture

Autoři

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.

Rok RIV

2011

Vydáno

26.04.2010

Nakladatel

IEEE Computer Society

Místo

Lille

ISBN

978-0-7695-4171-6

Kniha

13th EUROMICRO Conference on Digital System Design, DSD'2010

Strany od

365

Strany do

372

Strany počet

8

BibTex

@inproceedings{BUT34654,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration",
  booktitle="13th EUROMICRO Conference on Digital System Design, DSD'2010",
  year="2010",
  pages="365--372",
  publisher="IEEE Computer Society",
  address="Lille",
  isbn="978-0-7695-4171-6"
}