Detail publikačního výsledku

Design and Optimization of ColdFire CPU Arithmetic Logical Unit

ADAMEC, F.; FRÝZA, T.

Originální název

Design and Optimization of ColdFire CPU Arithmetic Logical Unit

Anglický název

Design and Optimization of ColdFire CPU Arithmetic Logical Unit

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

This article describes design of ColdFire microprocessor ALU (Arithmetic Logical Unit) in VHDL language and presents an optimization to obtain maximum performance in Xilinx Virtex IV FPGA. The basic function of ALU is explained. There are described the instructions which any ALU must handle and some possibility how to design it. The advantages and disadvantages of performance are obtained as well.

Anglický abstrakt

This article describes design of ColdFire microprocessor ALU (Arithmetic Logical Unit) in VHDL language and presents an optimization to obtain maximum performance in Xilinx Virtex IV FPGA. The basic function of ALU is explained. There are described the instructions which any ALU must handle and some possibility how to design it. The advantages and disadvantages of performance are obtained as well.

Klíčová slova

Arithmetic Logical Unit; VHDL; FPGA; instructions

Klíčová slova v angličtině

Arithmetic Logical Unit; VHDL; FPGA; instructions

Autoři

ADAMEC, F.; FRÝZA, T.

Rok RIV

2010

Vydáno

11.06.2009

Místo

Lodz (Poland)

ISBN

978-83-928756-0-4

Kniha

Proceedings of 16th International Conference Mixed Design of Integrated Circuits and Systems

Strany od

699

Strany do

702

Strany počet

4

BibTex

@inproceedings{BUT32734,
  author="Filip {Adamec} and Tomáš {Frýza}",
  title="Design and Optimization of ColdFire CPU Arithmetic Logical Unit",
  booktitle="Proceedings of 16th International Conference Mixed Design of Integrated Circuits and Systems",
  year="2009",
  pages="699--702",
  address="Lodz (Poland)",
  isbn="978-83-928756-0-4"
}