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Detail publikačního výsledku
ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.
Originální název
Power Conscious RTL Test Scheduling
Anglický název
Druh
Stať ve sborníku mimo WoS a Scopus
Originální abstrakt
In the paper, a methodology of power conscious RTL testscheduling is described. The methodology is based on thefact that circuit under analysis (CUA) is partitioned intotestable blocks (TB), the information about the partitioningis the input information for the methodology. TBs aremapped into AMI platform, for each TB the sequences oftest vectors are then derived, a professional tool is usedfor this purpose. The sequences of test vectors are then reorderedwith the goal to reduce power consumption duringtest application by reducing switching activities. The powerconsumption estimation is combined with the implementedplatform which allows to gain more precise results. Thevalues of TBs power consumption are then used in RTL testscheduling methodology. The goal is to find test schedulewith lowest test application time and lower power consumptionthan the required maximal value.
Anglický abstrakt
Klíčová slova
Test scheduling, testable block, power consumption, test vectors reordering, integer linear programming
Klíčová slova v angličtině
Autoři
Rok RIV
2010
Vydáno
02.06.2008
Nakladatel
IEEE Computer Society
Místo
Los Alamitos
ISBN
978-0-7695-3277-6
Kniha
Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools
Strany od
721
Strany do
728
Strany počet
8
URL
https://www.fit.vut.cz/research/publication/8700/
BibTex
@inproceedings{BUT30497, author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}", title="Power Conscious RTL Test Scheduling", booktitle="Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools", year="2008", pages="721--728", publisher="IEEE Computer Society", address="Los Alamitos", isbn="978-0-7695-3277-6", url="https://www.fit.vut.cz/research/publication/8700/" }
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