Detail publikačního výsledku

Design of Phase Locked-Loop for Very Slow Sine-Wave Signals

HÁZE, J.; VRBA, R.; PROKOP, R.

Originální název

Design of Phase Locked-Loop for Very Slow Sine-Wave Signals

Anglický název

Design of Phase Locked-Loop for Very Slow Sine-Wave Signals

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

Anglický abstrakt

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

Klíčová slova

phase locked-loop

Klíčová slova v angličtině

phase locked-loop

Autoři

HÁZE, J.; VRBA, R.; PROKOP, R.

Rok RIV

2010

Vydáno

16.01.2008

Nakladatel

IEEE

Místo

Cancun

ISBN

978-0-7695-3105-2

Kniha

Proceedings of IEEE International Conference on Systems ICONS 2008

Strany od

67

Strany do

71

Strany počet

5

BibTex

@inproceedings{BUT28637,
  author="Jiří {Háze} and Radimír {Vrba} and Roman {Prokop}",
  title="Design of Phase Locked-Loop for Very Slow Sine-Wave Signals",
  booktitle="Proceedings of IEEE International Conference on Systems ICONS 2008",
  year="2008",
  pages="67--71",
  publisher="IEEE",
  address="Cancun",
  isbn="978-0-7695-3105-2"
}