VHDL Design of Educational, Modern and Open-Architecture CPU

VHDL Design of Educational, Modern and Open-Architecture CPU

Stať ve sborníku mimo WoS a Scopus

The paper deals with design of a modern, open-architecture CPU utilizable for educational

purposes. It is expected that use of the CPU in the educational process will greatly contribute

to deeper understanding of key-topics taught in the area of modern architectures. Our

CPU is based on the Von-Neumann architecture, equipped with a five-stage pipeline, cache

memory unit and simple branch prediction unit. The architecture is designed in VHDL including

set of 16 instructions. Rich variety of educative tasks can be performed by means

of the CPU. It has been both successfully simulated in ModelSim and synthesized in Precision

RTL Synthesis in order to be implemented in FPGA and utilized in practice as a real

working CPU.

The paper deals with design of a modern, open-architecture CPU utilizable for educational

purposes. It is expected that use of the CPU in the educational process will greatly contribute

to deeper understanding of key-topics taught in the area of modern architectures. Our

CPU is based on the Von-Neumann architecture, equipped with a five-stage pipeline, cache

memory unit and simple branch prediction unit. The architecture is designed in VHDL including

set of 16 instructions. Rich variety of educative tasks can be performed by means

of the CPU. It has been both successfully simulated in ModelSim and synthesized in Precision

RTL Synthesis in order to be implemented in FPGA and utilized in practice as a real

working CPU.

VHDL, pipeline, CPU, cache, prediction unit

VHDL, pipeline, CPU, cache, prediction unit

STRAKA, M.

15.05.2007

Brno University of Technology

Brno

978-80-214-3410-3

Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4

457

461

5

https://www.fit.vut.cz/research/publication/8339/

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