Detail publikace

TCAD simulation of drain-induced barrier lowering

RECMAN Milan

Originální název

TCAD simulation of drain-induced barrier lowering

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

For short channel MOSFETs, the threshold voltage is reduced if the drain bias is increased and this short-channel effect (SCE) is known as drain-induced barrier lowering (DIBL). The contribution deals with TCAD simulation of DIBL. The method to extract the threshold voltage reduction and the subthreshold current increase due to DIBL is described. The experiment contains five different NMOSFET device simulations in order to illustrate drain-induced barrier lowering. The simulations are run under GENESISe. The tool flow starts with the device editor MDRAW followed by device simulator DESSIS and visualization and extraction tool INSPECT.

Klíčová slova

Device simulation, Electrical simulation, Parameter extraction, Device modeling, Curve fitting, Device optimization. 2D, Threshold voltage, Drain-induced barrier lowering.

Autoři

RECMAN Milan

Vydáno

1. 1. 2006

Nakladatel

Nakl. Novotný

Místo

Brno

ISBN

960-8025-99-8

Kniha

Electronic System Design 2006, Socrates International Conference Proceedings Chania, October 16 – 17, 2006, Greece

Strany od

76

Strany do

79

Strany počet

4

BibTex

@inproceedings{BUT24694,
  author="Milan {Recman}",
  title="TCAD simulation of drain-induced barrier lowering",
  booktitle="Electronic System Design 2006, Socrates International Conference Proceedings Chania, October 16 – 17, 2006, Greece",
  year="2006",
  pages="4",
  publisher="Nakl. Novotný",
  address="Brno",
  isbn="960-8025-99-8"
}