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KUBÍČEK, M.; KOVÁČ, M.
Originální název
Efficient Implementation of Clock and Data Recovery
Anglický název
Druh
Stať ve sborníku v databázi WoS či Scopus
Originální abstrakt
Clock and data recovery (CDR) is very common operation in modern communication systems. Data are usually transmitted without corresponding clock signal because it is inefficient and sometimes even impossible. Then it is necessary to recover a replica of the original clock signal on the receiver side. The replicated clock signal is derived from the incoming data signal and must have the same frequency and phase as the original one (rising edge of the clock must appear in the middle of the data bit). CDR can be managed in several ways depending strongly on the desired data rate. This paper describes possible solutions of CDR at data rates from about 100 Mb/s to several hundreds of Mb/s (the lower limit is only in terms of cost efficiency, not in capabilities, [3]).
Anglický abstrakt
Klíčová slova
Clock recovery, FPGA, VHDL, CDR
Klíčová slova v angličtině
Autoři
Vydáno
01.01.2007
Nakladatel
University of Miskolc
Místo
University of Miskolc, Hungary
ISBN
978-963-661-783-7
Kniha
Proceedings of the 6th International Conference of PhD Students
Strany od
289
Strany do
292
Strany počet
4
Plný text v Digitální knihovně
http://hdl.handle.net/
BibTex
@inproceedings{BUT23825, author="Michal {Kubíček} and Michal {Kováč}", title="Efficient Implementation of Clock and Data Recovery", booktitle="Proceedings of the 6th International Conference of PhD Students", year="2007", number="1", pages="289--292", publisher="University of Miskolc", address="University of Miskolc, Hungary", isbn="978-963-661-783-7" }