Detail publikačního výsledku

Combinational Divider in FPGA

KOLOUCH, J.

Originální název

Combinational Divider in FPGA

Anglický název

Combinational Divider in FPGA

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.

Anglický abstrakt

The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.

Klíčová slova

arithmetic functions, combinational logic, integer division, synthesis, FPGA, propagation delay, resource consumption

Klíčová slova v angličtině

arithmetic functions, combinational logic, integer division, synthesis, FPGA, propagation delay, resource consumption

Autoři

KOLOUCH, J.

Vydáno

24.04.2007

Nakladatel

Brno University of Technology

Místo

Brno

ISBN

1-4244-0821-0

Kniha

Proceedings of 17th International Conference Radioelektronika 2007

Strany od

69

Strany do

73

Strany počet

4

Plný text v Digitální knihovně

http://hdl.handle.net/

BibTex

@inproceedings{BUT23624,
  author="Jaromír {Kolouch}",
  title="Combinational Divider in FPGA",
  booktitle="Proceedings of 17th International Conference Radioelektronika 2007",
  year="2007",
  pages="69--73",
  publisher="Brno University of Technology",
  address="Brno",
  isbn="1-4244-0821-0"
}