Detail publikačního výsledku

Test Scheduling for SOC under Power Constraints

ŠKARVADA, J.

Originální název

Test Scheduling for SOC under Power Constraints

Anglický název

Test Scheduling for SOC under Power Constraints

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research.

Anglický abstrakt

The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research.

Klíčová slova

test scheduling, power constraint, test application conflict graph, genetic algorithm

Klíčová slova v angličtině

test scheduling, power constraint, test application conflict graph, genetic algorithm

Autoři

ŠKARVADA, J.

Vydáno

20.04.2006

Nakladatel

Czech Technical University Publishing House

Místo

Prague

ISBN

1-4244-0184-4

Kniha

Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

Strany od

91

Strany do

93

Strany počet

3

BibTex

@inproceedings{BUT22187,
  author="Jaroslav {Škarvada}",
  title="Test Scheduling for SOC under Power Constraints",
  booktitle="Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2006",
  pages="91--93",
  publisher="Czech Technical University Publishing House",
  address="Prague",
  isbn="1-4244-0184-4"
}