Detail publikačního výsledku

RT Level Testability Analysis In PROLOG Enviroment

KOTÁSEK, Z.; ZBOŘIL, F.

Originální název

RT Level Testability Analysis In PROLOG Enviroment

Anglický název

RT Level Testability Analysis In PROLOG Enviroment

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

The paper deals with the principles of the RT level testability analysis. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described in detail.

Anglický abstrakt

The paper deals with the principles of the RT level testability analysis. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described in detail.

Klíčová slova

RT Level Testability Analysis, RTL Circuit Transformation, PROLOG

Klíčová slova v angličtině

RT Level Testability Analysis, RTL Circuit Transformation, PROLOG

Autoři

KOTÁSEK, Z.; ZBOŘIL, F.

Vydáno

01.01.1997

Nakladatel

Marq software s.r.o.

Místo

Ostrava

ISBN

80-85988-19-4

Kniha

Proceedings of the DDECS'97

Strany od

47

Strany do

52

Strany počet

6

BibTex

@inproceedings{BUT191448,
  author="Zdeněk {Kotásek} and František {Zbořil}",
  title="RT Level Testability Analysis In  PROLOG Enviroment",
  booktitle="Proceedings of the  DDECS'97",
  year="1997",
  pages="47--52",
  publisher="Marq software s.r.o.",
  address="Ostrava",
  isbn="80-85988-19-4"
}