Detail publikačního výsledku

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

JEDLIČKA, P.; HAJNÝ, J.

Originální název

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Anglický název

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

CRYSTALS-Kyber is one of the finalists of the National Institute of Standards and Technology (NIST) post-quantum cryptography competition. In this paper, we deal with effective hardware-accelerated implementations of components intended for the use in the FPGA implementation of the above-mentioned lattice-based cryptography scheme. The discussed components are NTT, inverse NTT, CBD and the Parse Algorithm. The improved implementation of NTT (NTT-1) requires 1189 (1568) Look-Up Tables (LUTs), 1469 (2161) Flip-Flops (FFs), 28 (50) Digital Signal Processing blocks (DSPs) and 1.5 (1.5) Block Memories (BRAMs). The latency of the design is 322 (334) clock cycles at the frequency 637 MHz which makes the presented NTT (NTT-1) implementations to be currently the fastest ones. The implementations of the sampling functions (CBD and Parse) requires less than 100 LUTs and FFs with maximum latency 5 clock cycles at the frequencies over 700 Mhz. All implementations has been synthesized for the Xilinx Virtex UltraScale+ architecture.

Anglický abstrakt

CRYSTALS-Kyber is one of the finalists of the National Institute of Standards and Technology (NIST) post-quantum cryptography competition. In this paper, we deal with effective hardware-accelerated implementations of components intended for the use in the FPGA implementation of the above-mentioned lattice-based cryptography scheme. The discussed components are NTT, inverse NTT, CBD and the Parse Algorithm. The improved implementation of NTT (NTT-1) requires 1189 (1568) Look-Up Tables (LUTs), 1469 (2161) Flip-Flops (FFs), 28 (50) Digital Signal Processing blocks (DSPs) and 1.5 (1.5) Block Memories (BRAMs). The latency of the design is 322 (334) clock cycles at the frequency 637 MHz which makes the presented NTT (NTT-1) implementations to be currently the fastest ones. The implementations of the sampling functions (CBD and Parse) requires less than 100 LUTs and FFs with maximum latency 5 clock cycles at the frequencies over 700 Mhz. All implementations has been synthesized for the Xilinx Virtex UltraScale+ architecture.

Klíčová slova

NTT, CBD, Parse, VHDL, FPGA, Kyber

Klíčová slova v angličtině

NTT, CBD, Parse, VHDL, FPGA, Kyber

Autoři

JEDLIČKA, P.; HAJNÝ, J.

Rok RIV

2023

Vydáno

26.04.2022

Nakladatel

Brno University of Technology, Faculty of Electrical Engineering and Communication

Místo

Brno

ISBN

978-80-214-6030-0

Kniha

Proceedings II of the 28th Conference STUDENT EEICT 2022 Selected Papers

Edice

1st

Strany od

297

Strany do

301

Strany počet

5

URL

https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2022_sbornik_2_v2.pdf

BibTex

@inproceedings{BUT177748,
  author="Petr {Jedlička} and Jan {Hajný}",
  title="VHDL-based implementation of CRYSTALS-Kyber components on FPGA",
  booktitle="Proceedings II of the 28th Conference STUDENT EEICT 2022 Selected Papers",
  year="2022",
  series="1st",
  pages="297--301",
  publisher="Brno University of Technology, Faculty of Electrical Engineering and Communication",
  address="Brno",
  isbn="978-80-214-6030-0",
  url="https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2022_sbornik_2_v2.pdf"
}