Detail publikace

VHDL-Based Implementation of NTT on FPGA

JEDLIČKA, P.

Originální název

VHDL-Based Implementation of NTT on FPGA

Anglický název

VHDL-Based Implementation of NTT on FPGA

Jazyk

en

Originální abstrakt

This paper is focused on the effective hardware-accelerated implementation of NTT (Number Theoretic Transform) and inverse NTT (NTT−1) on FPGA (Field Programmable Gate Array). The discussed implementation is intended for the use in the lattice-based cryptography schemes, e.g. CRYSTALS-Dilithium digital signature scheme which is one of the finalists of the third round in the post-quantum standardization process under the auspices of NIST (The National Institute of Standards and Technology). The implementation of NTT (NTT−1) requires 1798 (2547) Look-Up Tables (LUTs), 2532 (3889) Flip-Flops (FFs) and 48 (84) Digital Signal Processing blocks (DSPs). The latency of the design is 502 (517) clock cycles at the frequency 637 MHz on Xilinx Virtex UltraScale+ architecture which makes the presented implementation to be currently the fastest one. Regarding the inverse NTT, this is the first implementation at all.

Anglický abstrakt

This paper is focused on the effective hardware-accelerated implementation of NTT (Number Theoretic Transform) and inverse NTT (NTT−1) on FPGA (Field Programmable Gate Array). The discussed implementation is intended for the use in the lattice-based cryptography schemes, e.g. CRYSTALS-Dilithium digital signature scheme which is one of the finalists of the third round in the post-quantum standardization process under the auspices of NIST (The National Institute of Standards and Technology). The implementation of NTT (NTT−1) requires 1798 (2547) Look-Up Tables (LUTs), 2532 (3889) Flip-Flops (FFs) and 48 (84) Digital Signal Processing blocks (DSPs). The latency of the design is 502 (517) clock cycles at the frequency 637 MHz on Xilinx Virtex UltraScale+ architecture which makes the presented implementation to be currently the fastest one. Regarding the inverse NTT, this is the first implementation at all.

Dokumenty

BibTex


@inproceedings{BUT172022,
  author="Petr {Jedlička}",
  title="VHDL-Based Implementation of NTT on FPGA",
  annote="This paper is focused on the effective hardware-accelerated implementation of NTT (Number Theoretic Transform) and inverse NTT (NTT−1) on FPGA (Field Programmable Gate Array). The discussed implementation is intended for the use in the lattice-based cryptography schemes, e.g. CRYSTALS-Dilithium digital signature scheme which is one of the finalists of the third round in the post-quantum standardization process under the auspices of NIST (The National Institute of Standards and Technology). The implementation of NTT (NTT−1) requires 1798 (2547) Look-Up Tables (LUTs), 2532 (3889) Flip-Flops (FFs) and 48 (84) Digital Signal Processing blocks (DSPs). The latency of the design is 502 (517) clock cycles at the frequency 637 MHz on Xilinx Virtex UltraScale+ architecture which makes the presented implementation to be currently the fastest one. Regarding the inverse NTT, this is the first implementation at all.",
  booktitle="Proceedings II of the 27th Conference STUDENT EEICT 2021",
  chapter="172022",
  edition="1st",
  howpublished="online",
  year="2021",
  month="july",
  pages="136--140",
  type="conference paper"
}