Detail publikace

Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage

PRÁŠEK, J. HOUŠKA, D. HRDÝ, R. HUBÁLEK, J. SCHMID, U.

Originální název

Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage

Anglický název

Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage

Jazyk

en

Originální abstrakt

In this paper we optimize cryogenic deep reactive ion etching processes to achieve the best aspect ratios of holes in a silicon substrate that is supposed to be used for fabrication of on-chip energy storage. By optimizing capacitively coupled plasma source power and oxygen flow, aspect ratio of 28:1 for holes of 2 µm in diameter was achieved. Bottling effect was suppressed by tuning capacitively coupled plasma, inductively coupled plasma sources and process pressure at the same time. The smoothness and purity of the hole walls are other parameters we investigate using atomic force microscopy and X-ray photoelectron spectroscopy.

Anglický abstrakt

In this paper we optimize cryogenic deep reactive ion etching processes to achieve the best aspect ratios of holes in a silicon substrate that is supposed to be used for fabrication of on-chip energy storage. By optimizing capacitively coupled plasma source power and oxygen flow, aspect ratio of 28:1 for holes of 2 µm in diameter was achieved. Bottling effect was suppressed by tuning capacitively coupled plasma, inductively coupled plasma sources and process pressure at the same time. The smoothness and purity of the hole walls are other parameters we investigate using atomic force microscopy and X-ray photoelectron spectroscopy.

Dokumenty

BibTex


@inproceedings{BUT161135,
  author="Jan {Prášek} and David {Houška} and Radim {Hrdý} and Jaromír {Hubálek} and Ulrich {Schmid}",
  title="Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage
",
  annote="In this paper we optimize cryogenic deep reactive ion etching processes to achieve the best aspect ratios of holes in a silicon substrate that is supposed to be used for fabrication of on-chip energy storage. By optimizing capacitively coupled plasma source power and oxygen flow, aspect ratio of 28:1 for holes of 2 µm in diameter was achieved. Bottling effect was suppressed by tuning capacitively coupled plasma, inductively coupled plasma sources and process pressure at the same time. The smoothness and purity of the hole walls are other parameters we investigate using atomic force microscopy and X-ray photoelectron spectroscopy.",
  address="IEEE Computer Society",
  booktitle="42st International Spring Seminar on Electronics Technology ISSE2019",
  chapter="161135",
  doi="10.1109/ISSE.2019.8810293",
  howpublished="electronic, physical medium",
  institution="IEEE Computer Society",
  year="2019",
  month="august",
  pages="1--6",
  publisher="IEEE Computer Society",
  type="conference paper"
}