Detail publikačního výsledku

Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage

PRÁŠEK, J.; HOUŠKA, D.; HRDÝ, R.; HUBÁLEK, J.; SCHMID, U.

Originální název

Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage

Anglický název

Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

In this paper we optimize cryogenic deep reactive ion etching processes to achieve the best aspect ratios of holes in a silicon substrate that is supposed to be used for fabrication of on-chip energy storage. By optimizing capacitively coupled plasma source power and oxygen flow, aspect ratio of 28:1 for holes of 2 µm in diameter was achieved. Bottling effect was suppressed by tuning capacitively coupled plasma, inductively coupled plasma sources and process pressure at the same time. The smoothness and purity of the hole walls are other parameters we investigate using atomic force microscopy and X-ray photoelectron spectroscopy.

Anglický abstrakt

In this paper we optimize cryogenic deep reactive ion etching processes to achieve the best aspect ratios of holes in a silicon substrate that is supposed to be used for fabrication of on-chip energy storage. By optimizing capacitively coupled plasma source power and oxygen flow, aspect ratio of 28:1 for holes of 2 µm in diameter was achieved. Bottling effect was suppressed by tuning capacitively coupled plasma, inductively coupled plasma sources and process pressure at the same time. The smoothness and purity of the hole walls are other parameters we investigate using atomic force microscopy and X-ray photoelectron spectroscopy.

Klíčová slova

dry etching; DRIE; cryogenic process; Bosch process; energy storage

Klíčová slova v angličtině

dry etching; DRIE; cryogenic process; Bosch process; energy storage

Autoři

PRÁŠEK, J.; HOUŠKA, D.; HRDÝ, R.; HUBÁLEK, J.; SCHMID, U.

Rok RIV

2020

Vydáno

26.08.2019

Nakladatel

IEEE Computer Society

Místo

Poland

ISBN

978-1-7281-1874-1

Kniha

42st International Spring Seminar on Electronics Technology ISSE2019

ISSN

2161-2536

Periodikum

Conference proceedings (International Spring Seminar on Electronics Technology)

Svazek

2019

Stát

Spojené státy americké

Strany od

1

Strany do

6

Strany počet

6

URL

https://ieeexplore.ieee.org/abstract/document/8810293

BibTex

@inproceedings{BUT161135,
  author="Jan {Prášek} and David {Houška} and Radim {Hrdý} and Jaromír {Hubálek} and Ulrich {Schmid}",
  title="Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage
",
  booktitle="42st International Spring Seminar on Electronics Technology ISSE2019",
  year="2019",
  journal="Conference proceedings (International Spring Seminar on Electronics Technology)",
  volume="2019",
  pages="1--6",
  publisher="IEEE Computer Society",
  address="Poland",
  doi="10.1109/ISSE.2019.8810293",
  isbn="978-1-7281-1874-1",
  url="https://ieeexplore.ieee.org/abstract/document/8810293"
}