Detail publikačního výsledku

Versatile Chirp Sine Generator on Fix-point FPGA

KUNZ, J.; BENEŠ, P.

Originální název

Versatile Chirp Sine Generator on Fix-point FPGA

Anglický název

Versatile Chirp Sine Generator on Fix-point FPGA

Druh

Článek WoS

Originální abstrakt

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.

Anglický abstrakt

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.

Klíčová slova

Linear Chirp Sine, Logarithm Chirp Sine, FPGA, Fix-point, Generation

Klíčová slova v angličtině

Linear Chirp Sine, Logarithm Chirp Sine, FPGA, Fix-point, Generation

Autoři

KUNZ, J.; BENEŠ, P.

Rok RIV

2021

Vydáno

31.12.2020

Nakladatel

Czech Technical University in Prague

Místo

Prague

ISSN

1805-2363

Periodikum

Acta Polytechnica

Svazek

60

Číslo

6

Stát

Česká republika

Strany od

462

Strany do

468

Strany počet

7

URL

https://ojs.cvut.cz/ojs/index.php/ap/article/view/6049

Plný text v Digitální knihovně

http://hdl.handle.net/11012/196548

BibTex

@article{BUT160854,
  author="Jan {Kunz} and Petr {Beneš}",
  title="Versatile Chirp Sine Generator on Fix-point FPGA",
  journal="Acta Polytechnica",
  year="2020",
  volume="60",
  number="6",
  pages="462--468",
  doi="10.14311/AP.2020.60.0462",
  issn="1210-2709",
  url="https://ojs.cvut.cz/ojs/index.php/ap/article/view/6049"
}

Dokumenty

6049-Article Text-22260-1-10-20210112