Detail publikace

Design of decimation filter for novel Sigma-Delta modulator

Lukas Fujcik, Thibault Mougel

Originální název

Design of decimation filter for novel Sigma-Delta modulator

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.

Klíčová slova

sigma-delta modulator, decimation filter

Autoři

Lukas Fujcik, Thibault Mougel

Rok RIV

2005

Vydáno

1. 1. 2005

Nakladatel

Technical University of Sofia

Místo

Bulgaria

ISBN

954-438-521-5

Kniha

THE FOURTEENT INTERNATIONAL SCIENTIFIC AND APPLIED SCIENCE CONFERENCE - ELECTRONICS ET'2005

Strany od

58

Strany do

63

Strany počet

6

BibTex

@inproceedings{BUT15924,
  author="Lukáš {Fujcik} and Thibault {Mougel}",
  title="Design of decimation filter for novel Sigma-Delta modulator",
  booktitle="THE FOURTEENT INTERNATIONAL SCIENTIFIC AND APPLIED SCIENCE CONFERENCE - ELECTRONICS ET'2005",
  year="2005",
  pages="6",
  publisher="Technical University of Sofia",
  address="Bulgaria",
  isbn="954-438-521-5"
}