Detail publikačního výsledku

Mitigating Curtaining Artifacts During Ga FIB TEM Lamella Preparation of a 14 nm FinFET Device

Andrey Denisyuk, Tomáš Hrnčíř, Jozef Vincenc Oboňa, Sharang, Martin Petrenec, Jan Michalička

Originální název

Mitigating Curtaining Artifacts During Ga FIB TEM Lamella Preparation of a 14 nm FinFET Device

Anglický název

Mitigating Curtaining Artifacts During Ga FIB TEM Lamella Preparation of a 14 nm FinFET Device

Druh

Článek WoS

Originální abstrakt

We report on the mitigation of curtaining artifacts during transmission electron microscopy (TEM) lamella preparation by means of a modified ion beam milling approach, which involves altering the incident angle of the Ga ions by rocking of the sample on a special stage. We applied this technique to TEM sample preparation of a state-of-the-art integrated circuit based on a 14-nm technology node. Site-specific lamellae with a thickness <15 nm were prepared by top-down Ga focused ion beam polishing through upper metal contacts. The lamellae were analyzed by means of high-resolution TEM, which showed a clear transistor structure and confirmed minimal curtaining artifacts. The results are compared with a standard inverted thinning preparation technique.

Anglický abstrakt

We report on the mitigation of curtaining artifacts during transmission electron microscopy (TEM) lamella preparation by means of a modified ion beam milling approach, which involves altering the incident angle of the Ga ions by rocking of the sample on a special stage. We applied this technique to TEM sample preparation of a state-of-the-art integrated circuit based on a 14-nm technology node. Site-specific lamellae with a thickness <15 nm were prepared by top-down Ga focused ion beam polishing through upper metal contacts. The lamellae were analyzed by means of high-resolution TEM, which showed a clear transistor structure and confirmed minimal curtaining artifacts. The results are compared with a standard inverted thinning preparation technique.

Klíčová slova

TEM sample lamella integrated circuit FinFET device

Klíčová slova v angličtině

TEM sample lamella integrated circuit FinFET device

Autoři

Andrey Denisyuk, Tomáš Hrnčíř, Jozef Vincenc Oboňa, Sharang, Martin Petrenec, Jan Michalička

Rok RIV

2019

Vydáno

17.06.2017

ISSN

1431-9276

Periodikum

MICROSCOPY AND MICROANALYSIS

Svazek

23

Číslo

3

Stát

Spojené státy americké

Strany od

484

Strany do

490

Strany počet

10

URL

https://www.cambridge.org/core/journals/microscopy-and-microanalysis/article/mitigating-curtaining-artifacts-during-ga-fib-tem-lamella-preparation-of-a-14-nm-finfet-device/072B2738731C7CE8D6680EF27CC69797

BibTex

@article{BUT149572,
  author="Jan {Michalička}",
  title="Mitigating Curtaining Artifacts During Ga FIB TEM Lamella Preparation of a 14 nm FinFET Device",
  journal="MICROSCOPY AND MICROANALYSIS",
  year="2017",
  volume="23",
  number="3",
  pages="484--490",
  doi="10.1017/S1431927617000241",
  issn="1431-9276",
  url="https://www.cambridge.org/core/journals/microscopy-and-microanalysis/article/mitigating-curtaining-artifacts-during-ga-fib-tem-lamella-preparation-of-a-14-nm-finfet-device/072B2738731C7CE8D6680EF27CC69797"
}