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Detail publikačního výsledku
POLEŠÁKOVÁ, Z.; JEŘÁBEK, J.
Originální název
A High Speed Middle Accuracy 9-bit SAR-ADC in 0.35-um CMOS for Sensor Application in Automotive Industry
Anglický název
Druh
Stať ve sborníku v databázi WoS či Scopus
Originální abstrakt
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 um, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality and the parameters of the SAR-ADC were verified in analog design environment Cadence Virtuoso. The parameters of the designed SAR-ADC are published in this paper.
Anglický abstrakt
Klíčová slova
SAR-ADC, CMOS technology, IC Design, Cadence Virtuoso, Automotive
Klíčová slova v angličtině
Autoři
Rok RIV
2018
Vydáno
06.07.2017
ISBN
978-1-5090-3981-4
Kniha
Proceedings of the 40th International Conference on Telecommunications and Signal Processing (TSP 2017)
Strany od
325
Strany do
329
Strany počet
5
URL
http://ieeexplore.ieee.org/document/8075997/
BibTex
@inproceedings{BUT137880, author="Zuzana {Bečková} and Jan {Jeřábek}", title="A High Speed Middle Accuracy 9-bit SAR-ADC in 0.35-um CMOS for Sensor Application in Automotive Industry", booktitle="Proceedings of the 40th International Conference on Telecommunications and Signal Processing (TSP 2017)", year="2017", pages="325--329", doi="10.1109/TSP.2017.8075997", isbn="978-1-5090-3981-4", url="http://ieeexplore.ieee.org/document/8075997/" }