Detail publikačního výsledku

Enhanced Architecture of FIR Filters Using Block Memories

PRISTACH, M.; DVOŘÁK, V.; FUJCIK, L.

Originální název

Enhanced Architecture of FIR Filters Using Block Memories

Anglický název

Enhanced Architecture of FIR Filters Using Block Memories

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

The paper presents an enhanced architecture of finite impulse response digital filters. The proposed architecture contains one multiply-accumulate unit and random access memory to store data. The architecture utilizes serial calculation to achieve minimum requirements on area. The architecture is suitable for implementation in application specific integrated circuits and field programmable gate arrays. The main advantages of the architecture are higher operating frequency, lower power consumption and smaller area utilization in particular cases.

Anglický abstrakt

The paper presents an enhanced architecture of finite impulse response digital filters. The proposed architecture contains one multiply-accumulate unit and random access memory to store data. The architecture utilizes serial calculation to achieve minimum requirements on area. The architecture is suitable for implementation in application specific integrated circuits and field programmable gate arrays. The main advantages of the architecture are higher operating frequency, lower power consumption and smaller area utilization in particular cases.

Klíčová slova

Digital signal processing; digital filter structures; finite impulse response; application specific integrated circuit; field-programmable gate array

Klíčová slova v angličtině

Digital signal processing; digital filter structures; finite impulse response; application specific integrated circuit; field-programmable gate array

Autoři

PRISTACH, M.; DVOŘÁK, V.; FUJCIK, L.

Rok RIV

2016

Vydáno

13.05.2015

Nakladatel

Institute of Electronics Silesian University of Technology

Místo

Krakov, Polsko

Kniha

13th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2015

ISSN

2405-8963

Periodikum

IFAC-PapersOnLine

Svazek

48

Číslo

4

Stát

Spojené království Velké Británie a Severního Irska

Strany od

306

Strany do

311

Strany počet

6

Plný text v Digitální knihovně

http://hdl.handle.net/

BibTex

@inproceedings{BUT115938,
  author="Marián {Pristach} and Vojtěch {Dvořák} and Lukáš {Fujcik}",
  title="Enhanced Architecture of FIR Filters Using Block Memories",
  booktitle="13th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2015",
  year="2015",
  journal="IFAC-PapersOnLine",
  volume="48",
  number="4",
  pages="306--311",
  publisher="Institute of Electronics Silesian University of Technology",
  address="Krakov, Polsko",
  doi="10.1016/j.ifacol.2015.07.052",
  issn="2405-8971"
}