Detail publikačního výsledku

Design Methodology of Configurable High Performance Packet Parser for FPGA

PUŠ, V.; KEKELY, L.; KOŘENEK, J.

Originální název

Design Methodology of Configurable High Performance Packet Parser for FPGA

Anglický název

Design Methodology of Configurable High Performance Packet Parser for FPGA

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

Anglický abstrakt

Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

Klíčová slova

Packet Parsing, Latency, FPGA

Klíčová slova v angličtině

Packet Parsing, Latency, FPGA

Autoři

PUŠ, V.; KEKELY, L.; KOŘENEK, J.

Rok RIV

2015

Vydáno

23.04.2014

Nakladatel

IEEE Computer Society

Místo

Warszawa

ISBN

978-1-4799-4558-0

Kniha

17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

Strany od

189

Strany do

194

Strany počet

6

URL

https://www.fit.vut.cz/research/publication/10616/

BibTex

@inproceedings{BUT111580,
  author="Viktor {Puš} and Lukáš {Kekely} and Jan {Kořenek}",
  title="Design Methodology of Configurable High Performance Packet Parser for FPGA",
  booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2014",
  pages="189--194",
  publisher="IEEE Computer Society",
  address="Warszawa",
  doi="10.1109/DDECS.2014.6868788",
  isbn="978-1-4799-4558-0",
  url="https://www.fit.vut.cz/research/publication/10616/"
}

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