Detail publikačního výsledku

On NFA-Split Architecture Optimizations

KOŠAŘ, V.; KOŘENEK, J.

Originální název

On NFA-Split Architecture Optimizations

Anglický název

On NFA-Split Architecture Optimizations

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

The NFA-Split architecture is an efficient approach to the mapping of regular expressions to the FPGA. However, the NFA-Split architecture has some drawbacks. The most significant are the high time complexity due to usage of determinisation to detect simultaneously active states. The other one is in some cases high consumption of BRAMs. The paper presents solutions of those drawbacks. According to the results up to 39 times overall speedup of  construction of the NFA-Split architecture was achieved. Reduction of utilized BRAMs is up to 97%.

Anglický abstrakt

The NFA-Split architecture is an efficient approach to the mapping of regular expressions to the FPGA. However, the NFA-Split architecture has some drawbacks. The most significant are the high time complexity due to usage of determinisation to detect simultaneously active states. The other one is in some cases high consumption of BRAMs. The paper presents solutions of those drawbacks. According to the results up to 39 times overall speedup of  construction of the NFA-Split architecture was achieved. Reduction of utilized BRAMs is up to 97%.

Klíčová slova

Regular expressions, Pattern matching, FPGA, NFA

Klíčová slova v angličtině

Regular expressions, Pattern matching, FPGA, NFA

Autoři

KOŠAŘ, V.; KOŘENEK, J.

Rok RIV

2015

Vydáno

23.04.2014

Nakladatel

IEEE Computer Society

Místo

Warsaw

ISBN

978-1-4799-4558-0

Kniha

2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Strany od

274

Strany do

277

Strany počet

4

BibTex

@inproceedings{BUT111523,
  author="Vlastimil {Košař} and Jan {Kořenek}",
  title="On NFA-Split Architecture Optimizations",
  booktitle="2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)",
  year="2014",
  pages="274--277",
  publisher="IEEE Computer Society",
  address="Warsaw",
  doi="10.1109/DDECS.2014.6868808",
  isbn="978-1-4799-4558-0"
}