Detail aplikovaného výsledku

ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays

DOBAI, R.

Originální název

ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays

Anglický název

ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays

Druh

Software

Abstrakt

ZyEHW is a joint hardware-software project for evolutionary design in the Xilinx Zynq-7000 field-programmable gate array. It contains (1) the hardware descriptions of the evolutionary design framework implemented in the programmable logic, (2) the software for both ARM processors of the Zynq platform and (3) the software required for generating the inputs and processing the outputs of the evolutionary design framework.
The evolutionary design framework is based on our developed architecture where the candidate solutions can be established and mutated by fine-grained partial reconfiguration of look-up tables. Our advanced control unit and the reduced routing ensures that six candidate solutions can be evaluated in parallel (in a XC7Z020 device) and at a very high operational frequency (a larger device would allow to evaluate even more candidate solutions in parallel).
The program code is deployed into one of the processors of Zynq-7000 and the evolutionary design framework into its programmable logic. Evolutionary on-line synthesis is performed by the other available processor. The functionality is transferred from software into hardware on-line, during runtime. This approach serves essentially the same purpose as high-level synthesis but the synthesis can be performed by a simple embedded computational platform and on-line.
Version v1.0 of ZyEHW includes the complete implementation of the case study for image filter evolution (noise filtering and edge detection).

Abstrakt aglicky

ZyEHW is a joint hardware-software project for evolutionary design in the Xilinx Zynq-7000 field-programmable gate array. It contains (1) the hardware descriptions of the evolutionary design framework implemented in the programmable logic, (2) the software for both ARM processors of the Zynq platform and (3) the software required for generating the inputs and processing the outputs of the evolutionary design framework.
The evolutionary design framework is based on our developed architecture where the candidate solutions can be established and mutated by fine-grained partial reconfiguration of look-up tables. Our advanced control unit and the reduced routing ensures that six candidate solutions can be evaluated in parallel (in a XC7Z020 device) and at a very high operational frequency (a larger device would allow to evaluate even more candidate solutions in parallel).
The program code is deployed into one of the processors of Zynq-7000 and the evolutionary design framework into its programmable logic. Evolutionary on-line synthesis is performed by the other available processor. The functionality is transferred from software into hardware on-line, during runtime. This approach serves essentially the same purpose as high-level synthesis but the synthesis can be performed by a simple embedded computational platform and on-line.
Version v1.0 of ZyEHW includes the complete implementation of the case study for image filter evolution (noise filtering and edge detection).

Klíčová slova

Evolutionary design, field-programmable gate array, high-level synthesis, on-line synthesis, hardware architecture, image filters

Klíčová slova anglicky

Evolutionary design, field-programmable gate array, high-level synthesis, on-line synthesis, hardware architecture, image filters

Umístění

Bitbucket (https://bitbucket.org/dobairoland/zyehw), Github

Licenční poplatek

Využití výsledku jiným subjektem je v některých případech možné bez nabytí licence

www

https://www.fit.vut.cz/research/product/381/