Real-time RFID Protocol Processing for SDR

Real-time RFID Protocol Processing for SDR

Software

The research team developed real-time algorithms and functions for fast data processing for an emulator of radio-frequency identification (RFID) devices. The work covers the implementation of receiver functions on the FPGA for a software defined radio (SDR) system, including the bit detector and the data decoder from complex IQ signals, and furthermore the implementation of transmitter functions on SDR FPGA, which consist of a data encoder and a waveform filter, providing baseband filtered waveform that fits the spectrum masks defined by EN 302 208 and FCC 15.247. All computations are done on-the-fly. The receiver uses a digital matched filter, which is able to detect very weak signals of passive backscatter tags. Due to the high tolerance of the link frequency of the expected signal, which is up to 22%, an adaptive algorithm has been developed for the receiver filter to lock to the actual data rate. The results include FPGA firmware (Verilog), software code (LabVIEW) and documentation of the implemented and tested algorithms and functions of the real-time data processing unit of the emulator. As a result, the emulator platform is capable of real-time handshaking with real RFID devices according the EPCglobal Class-1 Generation-2 standard.

The research team developed real-time algorithms and functions for fast data processing for an emulator of radio-frequency identification (RFID) devices. The work covers the implementation of receiver functions on the FPGA for a software defined radio (SDR) system, including the bit detector and the data decoder from complex IQ signals, and furthermore the implementation of transmitter functions on SDR FPGA, which consist of a data encoder and a waveform filter, providing baseband filtered waveform that fits the spectrum masks defined by EN 302 208 and FCC 15.247. All computations are done on-the-fly. The receiver uses a digital matched filter, which is able to detect very weak signals of passive backscatter tags. Due to the high tolerance of the link frequency of the expected signal, which is up to 22%, an adaptive algorithm has been developed for the receiver filter to lock to the actual data rate. The results include FPGA firmware (Verilog), software code (LabVIEW) and documentation of the implemented and tested algorithms and functions of the real-time data processing unit of the emulator. As a result, the emulator platform is capable of real-time handshaking with real RFID devices according the EPCglobal Class-1 Generation-2 standard.

RFID, SDR, real-time, Gen2

RFID, SDR, real-time, Gen2

CISC Semiconductor GmbH, Lakeside B07, Klagenfurt, A-9020, Austria; http://www.cisc.at/contact_rf.html

výsledek využívá pouze poskytovatel

K využití výsledku jiným subjektem je vždy nutné nabytí licence

http://www.urel.feec.vutbr.cz/web_documents/software/2013/Povalac_cisc_sw_cz.pdf