intMAN: Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

intMAN: Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

Prototyp

Prototype of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to analyze all interrupt stimuli and decide whether they should be forwarded do the system or temporarily deferred. The hardware is ready to buffer interrupt requests until the system is underloaded or running an activity having lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into FPGA devices from the Xilinx Spartan-6 family.

Prototype of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to analyze all interrupt stimuli and decide whether they should be forwarded do the system or temporarily deferred. The hardware is ready to buffer interrupt requests until the system is underloaded or running an activity having lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into FPGA devices from the Xilinx Spartan-6 family.

task, scheduling, real time, system, embedded, load, monitoring, interrupt management, excessive interrupt rate, overload prevention, FPGA, Xilinx, Spartan-6, VHDL

task, scheduling, real time, system, embedded, load, monitoring, interrupt management, excessive interrupt rate, overload prevention, FPGA, Xilinx, Spartan-6, VHDL

Ústav počítačových systémů, Fakulta informačních technologií Vysokého učení technického v Brně, Božetěchova 2, 612 66 Brno

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https://www.fit.vut.cz/research/product/303/

Experimentální platforma
Schéma zapojení
Platforma - stackup
VHDL - zdrojové texty a dokumentace