Efficient Reverse Converter and Residue Comparator Based on a Novel Algorithm for Reverse Conversion

Efficient Reverse Converter and Residue Comparator Based on a Novel Algorithm for Reverse Conversion

Článek recenzovaný mimo WoS a Scopus

This paper presents a novel algorithm for performing reverse conversion in the residue number system (RNS) based on the moduli set {2n – 1, 2n, 2n + 1}. The majority of the papers regarding the reverse converters are principally based on one of the following algorithms; the mixed radix conversion (MRC), the Chinese remainder theorem (CRT) and the new Chinese remainder theorems (new CRTs). The proposed algorithm is simpler and does not require multiplicative inverses neither performing multiplication operations. Moreover, a residue to binary converter and a residue comparator based on the proposed algorithm are presented too. The proposed components provide attractive characteristics in systems with medium to large dynamic ranges. They can operate at considerably higher frequencies than their counterparts can. The proposed reverse converter and residue comparator are implemented on Spartan-3E FPGA. The implementation results and comparisons proved the efficiency and superiority of the proposed algorithm.

This paper presents a novel algorithm for performing reverse conversion in the residue number system (RNS) based on the moduli set {2n – 1, 2n, 2n + 1}. The majority of the papers regarding the reverse converters are principally based on one of the following algorithms; the mixed radix conversion (MRC), the Chinese remainder theorem (CRT) and the new Chinese remainder theorems (new CRTs). The proposed algorithm is simpler and does not require multiplicative inverses neither performing multiplication operations. Moreover, a residue to binary converter and a residue comparator based on the proposed algorithm are presented too. The proposed components provide attractive characteristics in systems with medium to large dynamic ranges. They can operate at considerably higher frequencies than their counterparts can. The proposed reverse converter and residue comparator are implemented on Spartan-3E FPGA. The implementation results and comparisons proved the efficiency and superiority of the proposed algorithm.

Residue number system, reverse converter, residue Comparator, {2n – 1, 2n, 2n + 1}, the new CRT - I

Residue number system, reverse converter, residue Comparator, {2n – 1, 2n, 2n + 1}, the new CRT - I

YOUNES, D.; ŠTEFFAN, P.

2014

31.07.2013

1694-0784

International Journal of Computer Science Issues

10

4

Mauricijská republika

23

30

7