Detail publikačního výsledku

Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

KUTÁLEK, V.; DVOŘÁK, V.

Originální název

Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

Anglický název

Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

Process- and thread-level parallelism is very often exploited inasynchronous processor pipelines for embedded applications, recently ona chip. The paper deals with simulation of pipelines with one or moreworkers in each pipeline stage. The number of workers can be adjustedto balance execution time of other stages so as to keep efficiencyhigh. Simulation-based prototyping of such pipeline processor farmsusing Transim tool can account for communication delays, multitasking,data-dependent variations in workload, CPUs with different speeds, etc.Simulation results for a given task divisible to a few subtasks ofarbitrary duration are presented as well as a particular example of apower of a matrix.

Anglický abstrakt

Process- and thread-level parallelism is very often exploited inasynchronous processor pipelines for embedded applications, recently ona chip. The paper deals with simulation of pipelines with one or moreworkers in each pipeline stage. The number of workers can be adjustedto balance execution time of other stages so as to keep efficiencyhigh. Simulation-based prototyping of such pipeline processor farmsusing Transim tool can account for communication delays, multitasking,data-dependent variations in workload, CPUs with different speeds, etc.Simulation results for a given task divisible to a few subtasks ofarbitrary duration are presented as well as a particular example of apower of a matrix.

Klíčová slova

Multiprocessor SoC, pipeline/farm architecture, performance prediction

Klíčová slova v angličtině

Multiprocessor SoC, pipeline/farm architecture, performance prediction

Autoři

KUTÁLEK, V.; DVOŘÁK, V.

Rok RIV

2011

Vydáno

22.04.2002

Nakladatel

Faculty of Information Technology BUT

Místo

Brno

ISBN

80-214-2094-4

Kniha

Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop

Strany od

296

Strany do

299

Strany počet

4

BibTex

@inproceedings{BUT9823,
  author="Vladimír {Kutálek} and Václav {Dvořák}",
  title="Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture",
  booktitle="Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop",
  year="2002",
  pages="296--299",
  publisher="Faculty of Information Technology BUT",
  address="Brno",
  isbn="80-214-2094-4"
}