Detail publikačního výsledku

Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA

STRAKA, M.; KAŠTIL, J.; NOVOTNÝ, J.; KOTÁSEK, Z.

Originální název

Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA

Anglický název

Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform.

Anglický abstrakt

In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform.

Klíčová slova

FPGA, fault tolerant, bus, multicore, reconfiguration, on-line checker, TMR

Klíčová slova v angličtině

FPGA, fault tolerant, bus, multicore, reconfiguration, on-line checker, TMR

Autoři

STRAKA, M.; KAŠTIL, J.; NOVOTNÝ, J.; KOTÁSEK, Z.

Rok RIV

2012

Vydáno

25.02.2011

Nakladatel

IEEE Computer Society

Místo

Cottbus

ISBN

978-1-4244-9753-9

Kniha

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

Strany od

397

Strany do

398

Strany počet

2

BibTex

@inproceedings{BUT76277,
  author="Martin {Straka} and Jan {Kaštil} and Jaroslav {Novotný} and Zdeněk {Kotásek}",
  title="Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  year="2011",
  pages="397--398",
  publisher="IEEE Computer Society",
  address="Cottbus",
  isbn="978-1-4244-9753-9"
}