Detail publikace

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

DVOŘÁK, V.

Originální název

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

Klíčová slova

Parallel Embedded Systems, Multiprocessor Simulation, Hardware Description Language

Autoři

DVOŘÁK, V.

Rok RIV

2001

Vydáno

1. 1. 2001

Nakladatel

Publishing House of Zielona Gora Technical University

Místo

Przytok near Zielona Gora, POLAND

ISBN

83-85911-62-6

Kniha

Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01

Strany od

103

Strany do

108

Strany počet

6

BibTex

@inproceedings{BUT5579,
  author="Václav {Dvořák}",
  title="Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study",
  booktitle="Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01",
  year="2001",
  pages="103--108",
  publisher="Publishing House of Zielona Gora Technical University",
  address="Przytok near Zielona Gora, POLAND",
  isbn="83-85911-62-6"
}