Detail publikačního výsledku

Verification of Digital Design Using Non-Synthesizable Description

KOLOUCH, J.

Originální název

Verification of Digital Design Using Non-Synthesizable Description

Anglický název

Verification of Digital Design Using Non-Synthesizable Description

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

A verification method suitable for lower-style HDL model development is presented. It allows the use of the try-and-correct method that can be advantageous in writing models intended for synthesis. It can be used in laboratory exercises with WebPACK software that is freely available on www pages of Xilinx.

Anglický abstrakt

A verification method suitable for lower-style HDL model development is presented. It allows the use of the try-and-correct method that can be advantageous in writing models intended for synthesis. It can be used in laboratory exercises with WebPACK software that is freely available on www pages of Xilinx.

Klíčová slova

HDL language, verification, simulation, FPGA

Klíčová slova v angličtině

HDL language, verification, simulation, FPGA

Autoři

KOLOUCH, J.

Vydáno

15.05.2002

Nakladatel

Slovak University of Technology in Bratislava

Místo

Bratislava

ISBN

80-227-1700-2

Kniha

Radioelektronika 2002, Conference Proceedings

Strany od

417

Strany do

420

Strany počet

4

BibTex

@inproceedings{BUT5248,
  author="Jaromír {Kolouch}",
  title="Verification of Digital Design Using Non-Synthesizable Description",
  booktitle="Radioelektronika 2002, Conference Proceedings",
  year="2002",
  pages="417--420",
  publisher="Slovak University of Technology in Bratislava",
  address="Bratislava",
  isbn="80-227-1700-2"
}