Detail publikačního výsledku

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.

Originální název

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Anglický název

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Druh

Článek recenzovaný mimo WoS a Scopus

Originální abstrakt

The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached.

Anglický abstrakt

The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached.

Klíčová slova

Testable block, Circuit partitioning, Test vectors reordering, Scan cells reordering, Low power

Klíčová slova v angličtině

Testable block, Circuit partitioning, Test vectors reordering, Scan cells reordering, Low power

Autoři

ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.

Rok RIV

2010

Vydáno

04.04.2008

Kniha

Microprocessors and Microsystems, Dependability and Testing of Modern Digital Systems

ISSN

0141-9331

Periodikum

Microprocessors and Microsystems

Svazek

32

Číslo

5

Stát

Nizozemsko

Strany od

296

Strany do

302

Strany počet

7

URL

http://dx.doi.org/10.1016/j.micpro.2008.03.002

BibTex

@article{BUT49469,
  author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}",
  title="Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties",
  journal="Microprocessors and Microsystems",
  year="2008",
  volume="32",
  number="5",
  pages="296--302",
  issn="0141-9331",
  url="http://dx.doi.org/10.1016/j.micpro.2008.03.002"
}