Detail publikačního výsledku

Evolutionary Functional Recovery in Virtual Reconfigurable Circuits

SEKANINA, L.

Originální název

Evolutionary Functional Recovery in Virtual Reconfigurable Circuits

Anglický název

Evolutionary Functional Recovery in Virtual Reconfigurable Circuits

Druh

Článek recenzovaný mimo WoS a Scopus

Originální abstrakt

A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices. 

Anglický abstrakt

A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices. 

Klíčová slova

hardware, logic design, reliability, reconfigurable circuit, evolutionary algorithm

Klíčová slova v angličtině

hardware, logic design, reliability, reconfigurable circuit, evolutionary algorithm

Autoři

SEKANINA, L.

Vydáno

30.07.2007

ISSN

1550-4832

Periodikum

ACM Journal on Emerging Technologies in Computing Systems

Svazek

3

Číslo

2

Stát

Spojené státy americké

Strany od

1

Strany do

22

Strany počet

22

URL

http://www.fit.vutbr.cz/~sekanina/publ/ject/ject07.pdf

BibTex

@article{BUT45162,
  author="Lukáš {Sekanina}",
  title="Evolutionary Functional Recovery in Virtual Reconfigurable Circuits",
  journal="ACM Journal on Emerging Technologies in Computing Systems",
  year="2007",
  volume="3",
  number="2",
  pages="1--22",
  issn="1550-4832",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ject/ject07.pdf"
}