Detail publikačního výsledku

Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.

Originální název

Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs

Anglický název

Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

Anglický abstrakt

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

Klíčová slova

fault tolerant, on-line checker, architecture, triple modular redundancy, duplex, FPGA, partial reconfiguration

Klíčová slova v angličtině

fault tolerant, on-line checker, architecture, triple modular redundancy, duplex, FPGA, partial reconfiguration

Autoři

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.

Rok RIV

2011

Vydáno

25.02.2010

Nakladatel

IEEE Computer Society

Místo

Wien

ISBN

978-1-4244-6610-8

Kniha

Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010

Strany od

173

Strany do

176

Strany počet

4

BibTex

@inproceedings{BUT34646,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs",
  booktitle="Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010",
  year="2010",
  pages="173--176",
  publisher="IEEE Computer Society",
  address="Wien",
  isbn="978-1-4244-6610-8"
}