PQC ASIC - All-Digital PLL Block

PQC ASIC - All-Digital PLL Block

Funkční vzorek

Designed ADPLL block is implemented as a functional specimen designed for clock generation within a security-oriented System-on-Chip (SoC) targeting post-quantum cryptography applications. The primary objective of the design is to achieve fast and reliable frequency locking while maintaining high resolution and operational robustness. The fully integrated architecture eliminates the need for external components, providing a self-contained and stable clock source suitable for secure hardware environments.

Designed ADPLL block is implemented as a functional specimen designed for clock generation within a security-oriented System-on-Chip (SoC) targeting post-quantum cryptography applications. The primary objective of the design is to achieve fast and reliable frequency locking while maintaining high resolution and operational robustness. The fully integrated architecture eliminates the need for external components, providing a self-contained and stable clock source suitable for secure hardware environments.

ADPLL, Frequency synthesis, Mixed-signal design, Fast lock, Hardware security

ADPLL, Frequency synthesis, Mixed-signal design, Fast lock, Hardware security

Výsledek je využíván vlastníkem