Detail publikačního výsledku

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

BRADÁČ, Z., VALACH, S.

Originální název

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

Anglický název

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

The present electronic industry achieves unusual expansion of communication technology based on high-speed serial interfaces. It is due to need higher bandwidth and performance, lower size, power consumption and device price. The article will be focused on a different approaches how to implement 10 GigaBit Ethernet physical layer in the FPGA based structures.

Anglický abstrakt

The present electronic industry achieves unusual expansion of communication technology based on high-speed serial interfaces. It is due to need higher bandwidth and performance, lower size, power consumption and device price. The article will be focused on a different approaches how to implement 10 GigaBit Ethernet physical layer in the FPGA based structures.

Klíčová slova v angličtině

FPGA, Ethernet, XGMII, XAUI, RocketIO, Combo6.

Autoři

BRADÁČ, Z., VALACH, S.

Vydáno

01.02.2006

Nakladatel

VUT Brno

Místo

Brno

ISBN

80-214-3130-X

Kniha

Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003

Strany od

427

Strany počet

6

BibTex

@inproceedings{BUT19451,
  author="Zdeněk {Bradáč} and Soběslav {Valach}",
  title="10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS",
  booktitle="Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003",
  year="2006",
  pages="6",
  publisher="VUT Brno",
  address="Brno",
  isbn="80-214-3130-X"
}