Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals from Sensors

Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals from Sensors

Článek WoS

Phase-Locked Loops (PLLs) are versatile electronic circuits that, among others, are used in various sensor applications (e.g., medical) for their ability to generate stable and precise clock signals. This paper introduces a novel PLL-based frequency demodulation system designed for processing very slow signals, ranging from a few Hz to several hundreds of Hz, with amplitudes in the order of several hundreds of millivolts. The system incorporates specialized analog multipliers tailored for essential PLL components, including the voltage-controlled oscillator, phase detector, loop filter with variable DC offset, and base-band filter, all optimized for the purpose of frequency demodulation. These multipliers were fabricated using the TSMC 0.18 µm, 1.8 V CMOS process. The primary design objectives are simplicity, reduced complexity, low power consumption (merely 15 mW), and versatility for applications in sensing engineering. To validate the functionality of the proposed PLL system under practical conditions, we present an example of electrocardiogram signal demodulation, demonstrating its operational performance.

Phase-Locked Loops (PLLs) are versatile electronic circuits that, among others, are used in various sensor applications (e.g., medical) for their ability to generate stable and precise clock signals. This paper introduces a novel PLL-based frequency demodulation system designed for processing very slow signals, ranging from a few Hz to several hundreds of Hz, with amplitudes in the order of several hundreds of millivolts. The system incorporates specialized analog multipliers tailored for essential PLL components, including the voltage-controlled oscillator, phase detector, loop filter with variable DC offset, and base-band filter, all optimized for the purpose of frequency demodulation. These multipliers were fabricated using the TSMC 0.18 µm, 1.8 V CMOS process. The primary design objectives are simplicity, reduced complexity, low power consumption (merely 15 mW), and versatility for applications in sensing engineering. To validate the functionality of the proposed PLL system under practical conditions, we present an example of electrocardiogram signal demodulation, demonstrating its operational performance.

CMOS multiplier, frequency modulation, loop filter, phase-locked loop, phase detector, voltage control oscillator.

CMOS multiplier, frequency modulation, loop filter, phase-locked loop, phase detector, voltage control oscillator.

SVOBODA, M.; ŠOTNER, R.; POLÁK, L.; JEŘÁBEK, J.; JAIKLA, W.; ANDRIUKAITIS, D.

2025

24.10.2024

IEEE

0018-9456

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT

2024

73

Spojené státy americké

1

12

12

https://ieeexplore.ieee.org/document/10648767