Detail publikace

New approach to the FPGA testing based on the Boundary Scan

KOTÁSEK, Z. TUPEC, P.

Originální název

New approach to the FPGA testing based on the Boundary Scan

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, a method enabling to verify the functionality of an FPGAdesign is presented. This method is based on the formal modelconstruction of the register transfer (RT) level digital circuit. Thisnew approach allows FPGA designers to debug and verify their hardwarebeing developed. A Boundary scan is used as a communication interface.As an input, a digital circuit structure at RT level designed using anyDfT technique is assumed.

Klíčová slova

JTAG, debugger, RT level, boundary scan

Autoři

KOTÁSEK, Z.; TUPEC, P.

Rok RIV

2004

Vydáno

11. 5. 2004

Nakladatel

Marq software s.r.o.

Místo

Ostrava

ISBN

80-85988-98-4

Kniha

Proceedings of 38th International Conference MOSIS'04

Strany od

120

Strany do

123

Strany počet

4

BibTex

@inproceedings{BUT16896,
  author="Zdeněk {Kotásek} and Pavel {Tupec}",
  title="New approach to the FPGA testing based on the Boundary Scan",
  booktitle="Proceedings of 38th International Conference MOSIS'04",
  year="2004",
  pages="120--123",
  publisher="Marq software s.r.o.",
  address="Ostrava",
  isbn="80-85988-98-4"
}