A Processor Optimization Framework for a Selected Application

A Processor Optimization Framework for a Selected Application

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A processor plays the main role in almost every electronics system. The use of a general purpose processor may not be profitable for a specific application, because the processor is designed for a wide set of applications. Application Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where one application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking its possible configurations of key parameters (number of registers, size of caches, instruction set modification, etc.). The paper also presents designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modification, the Codasip Studio tool is used. It allows to generate all tools needed for compilation, simulation, and hardware mapping which are needed in process of ASIP design. The experiments are carried on RISC-V (Reduced Instruction Set Computing) processor described in Codasip Studio.

A processor plays the main role in almost every electronics system. The use of a general purpose processor may not be profitable for a specific application, because the processor is designed for a wide set of applications. Application Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where one application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking its possible configurations of key parameters (number of registers, size of caches, instruction set modification, etc.). The paper also presents designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modification, the Codasip Studio tool is used. It allows to generate all tools needed for compilation, simulation, and hardware mapping which are needed in process of ASIP design. The experiments are carried on RISC-V (Reduced Instruction Set Computing) processor described in Codasip Studio.

Processor optimization, ASIP, Codasip Studio, embedded system, RISC-V

Processor optimization, ASIP, Codasip Studio, embedded system, RISC-V

PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z.

2019

14.09.2018

IEEE Computer Society

Kazan

978-1-5386-5710-2

Proceedings of IEEE East-West Design & Test Symposium

564

574

11

https://www.fit.vut.cz/research/publication/11689/

http://hdl.handle.net/

EWDTS18_Podivinsky_et_al_SBORNIK