Detail publikačního výsledku

Packet Classification Algorithms

PUŠ, V.

Originální název

Packet Classification Algorithms

Anglický název

Packet Classification Algorithms

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in
hardware can achieve multigigabit speeds,
but they suffer with great memory overhead.
This paper presents three packet classification algorithms
with strong potential
for acceleration in ASIC or FPGA,
while the memory requirements are kept reasonably low.

Anglický abstrakt

As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in
hardware can achieve multigigabit speeds,
but they suffer with great memory overhead.
This paper presents three packet classification algorithms
with strong potential
for acceleration in ASIC or FPGA,
while the memory requirements are kept reasonably low.

Klíčová slova

Packet Classification, FPGA, Optimization

Klíčová slova v angličtině

Packet Classification, FPGA, Optimization

Autoři

PUŠ, V.

Rok RIV

2012

Vydáno

12.09.2011

Nakladatel

Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava

Místo

Stará Lesná

ISBN

978-80-227-3552-0

Kniha

Počítačové architektury a diagnostika

Strany od

157

Strany do

162

Strany počet

6

BibTex

@inproceedings{BUT76363,
  author="Viktor {Puš}",
  title="Packet Classification Algorithms",
  booktitle="Počítačové architektury a diagnostika",
  year="2011",
  pages="157--162",
  publisher="Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava",
  address="Stará Lesná",
  isbn="978-80-227-3552-0"
}