Publication result detail

Packet Classification Algorithms

PUŠ, V.

Original Title

Packet Classification Algorithms

English Title

Packet Classification Algorithms

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in
hardware can achieve multigigabit speeds,
but they suffer with great memory overhead.
This paper presents three packet classification algorithms
with strong potential
for acceleration in ASIC or FPGA,
while the memory requirements are kept reasonably low.

English abstract

As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in
hardware can achieve multigigabit speeds,
but they suffer with great memory overhead.
This paper presents three packet classification algorithms
with strong potential
for acceleration in ASIC or FPGA,
while the memory requirements are kept reasonably low.

Keywords

Packet Classification, FPGA, Optimization

Key words in English

Packet Classification, FPGA, Optimization

Authors

PUŠ, V.

RIV year

2012

Released

12.09.2011

Publisher

Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava

Location

Stará Lesná

ISBN

978-80-227-3552-0

Book

Počítačové architektury a diagnostika

Pages from

157

Pages to

162

Pages count

6

BibTex

@inproceedings{BUT76363,
  author="Viktor {Puš}",
  title="Packet Classification Algorithms",
  booktitle="Počítačové architektury a diagnostika",
  year="2011",
  pages="157--162",
  publisher="Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava",
  address="Stará Lesná",
  isbn="978-80-227-3552-0"
}