Detail publikace

Optimization of BDD-based Approximation Error Metrics Calculations

MRÁZEK, V.

Originální název

Optimization of BDD-based Approximation Error Metrics Calculations

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

Software methods introduced for automated design of approximate implementations of arithmetic circuits rely on fast and accurate evaluation of approximate candidate implementations. To accelerate the evaluation of circuit error, we propose four novel algorithms for the exact worst-case and mean absolute error analysis based on Binary Decision Diagrams. As these algorithms do not compute any absolute values in the characteristic function, which basically compares a candidate approximate circuit with a golden circuit, the error evaluation is significantly faster than the standard BDD-based error analysis. On average, the proposed algorithms are three times faster (in some cases, 30 times faster) than the baseline for 8- to 32-bit approximate adders. These results were obtained from more than 49 thousand runs with different configurations of the method. The proposed error evaluation algorithms are available as an open-source software https://github.com/ehw-fit/bdd-evaluation.

Klíčová slova

approximate computing, error evaluation, relaxed equivalence checking

Autoři

MRÁZEK, V.

Vydáno

8. 7. 2022

Nakladatel

Institute of Electrical and Electronics Engineers

Místo

Paphos

ISBN

978-1-6654-6605-9

Kniha

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)

Strany od

86

Strany do

91

Strany počet

6

BibTex

@inproceedings{BUT177787,
  author="Vojtěch {Mrázek}",
  title="Optimization of BDD-based Approximation Error Metrics Calculations",
  booktitle="IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)",
  year="2022",
  pages="86--91",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Paphos",
  doi="10.1109/ISVLSI54635.2022.00028",
  isbn="978-1-6654-6605-9"
}