EA-based refactoring of mapped logic circuits

EA-based refactoring of mapped logic circuits

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The increasing complexity of the designs and prob-lematic scalability of original representations led to a shift ininternal representations used in logic synthesis and optimization. Heterogeneous representations were replaced with homogeneous intermediate representations. And-inverter graph (AIG) has been identified as the most promising structure for scalable logic optimization and many efficient algorithms were implemented on top of it. However, the inability of AIG to efficiently represent XOR gates together with heuristic nature of logic optimization algorithms  leads to some inefficiency causing that the logic can be further minimized even after it has been mapped. This paper presents an optimization technique based on refactoring targeting mapped combinational circuits. It iteratively selects large cones of logic, optimizes them and returns them back to the original structure provided that there is an improvement in some metric.Performance of the method is evaluated on a set of complex academic and industrial benchmarks. We show that a 9.2%reduction in area can be achieved in average compared to thehighly optimized results obtained using the academic state-of-the-art synthesis tool. In average, more than 14% reduction was observed for arithmetic circuits.

The increasing complexity of the designs and prob-lematic scalability of original representations led to a shift ininternal representations used in logic synthesis and optimization. Heterogeneous representations were replaced with homogeneous intermediate representations. And-inverter graph (AIG) has been identified as the most promising structure for scalable logic optimization and many efficient algorithms were implemented on top of it. However, the inability of AIG to efficiently represent XOR gates together with heuristic nature of logic optimization algorithms  leads to some inefficiency causing that the logic can be further minimized even after it has been mapped. This paper presents an optimization technique based on refactoring targeting mapped combinational circuits. It iteratively selects large cones of logic, optimizes them and returns them back to the original structure provided that there is an improvement in some metric.Performance of the method is evaluated on a set of complex academic and industrial benchmarks. We show that a 9.2%reduction in area can be achieved in average compared to thehighly optimized results obtained using the academic state-of-the-art synthesis tool. In average, more than 14% reduction was observed for arithmetic circuits.

Cartesian Genetic Programming, Resynthesis, Logic optimization

Cartesian Genetic Programming, Resynthesis, Logic optimization

KOCNOVÁ, J.; VAŠÍČEK, Z.

2020

01.05.2019

IEEE Computer Society Press

Red Hook, NY

978-1-7281-0397-6

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

1

5

5

https://www.fit.vut.cz/research/publication/11847/

08702084