Evolutionary Functional Approximation of Circuits Implemented into FPGAs

Evolutionary Functional Approximation of Circuits Implemented into FPGAs

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In many applications it is acceptable to allow a smallerror in the result if significant improvements are obtained interms of performance, area or energy efficiency. Exploiting thisprinciple is particularly important for FPGA-based solutions thatare inherently subject to many resources- oriented constraints.This paper devises an automated method that enables to approximatecircuit components which are often implemented inmultiple instances in FPGA-based accelerators. The approximation process starts with a fully functional gate-level circuit, whichis approximated by means of Cartesian Genetic Programmingreflecting the error metric and constraints formulated by theuser. The evolved circuits are then implemented for a particularFPGA by common FPGA synthesis and optimization tools. It isshown using five different FPGA tools, that the approximationsobtained by CGP working at the gate level are preserved at thelevel look-up tables of FPGAs. The proposed method is evaluatedin the task of 8-bit adder, 8-bit multiplier, 9-input median and 25-input median approximation. 

In many applications it is acceptable to allow a smallerror in the result if significant improvements are obtained interms of performance, area or energy efficiency. Exploiting thisprinciple is particularly important for FPGA-based solutions thatare inherently subject to many resources- oriented constraints.This paper devises an automated method that enables to approximatecircuit components which are often implemented inmultiple instances in FPGA-based accelerators. The approximation process starts with a fully functional gate-level circuit, whichis approximated by means of Cartesian Genetic Programmingreflecting the error metric and constraints formulated by theuser. The evolved circuits are then implemented for a particularFPGA by common FPGA synthesis and optimization tools. It isshown using five different FPGA tools, that the approximationsobtained by CGP working at the gate level are preserved at thelevel look-up tables of FPGAs. The proposed method is evaluatedin the task of 8-bit adder, 8-bit multiplier, 9-input median and 25-input median approximation. 

functional approximation
evolutionary algorithm
equivalence
FPGA synthesis

functional approximation
evolutionary algorithm
equivalence
FPGA synthesis

VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L.

2017

15.08.2016

Institute of Electrical and Electronics Engineers

Athens

978-1-5090-4240-1

2016 IEEE Symposium Series on Computational Intelligence

1

8

8

https://www.fit.vut.cz/research/publication/11243/

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