Detail publikačního výsledku

Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols

GROCHOL, D.; SEKANINA, L.; KOŘENEK, J.; ŽÁDNÍK, M.; KOŠAŘ, V.

Originální název

Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols

Anglický název

Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols

Druh

Článek WoS

Originální abstrakt

The evolutionary design can produce fast and efficient implementations of digital circuits. It is shown in this paper how evolved circuits, optimized for the latency and area, can increase the throughput of a manually designed classifier of application protocols. The classifier is intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array (FPGA). The classification is performed using the first packet carrying the application payload. The improvements in latency (and area) obtained by Cartesian genetic programming are validated using a professional FPGA design tool. The quality of classification is evaluated by means of real network data. All results are compared with commonly used classifiers based on regular expressions describing application protocols.

Anglický abstrakt

The evolutionary design can produce fast and efficient implementations of digital circuits. It is shown in this paper how evolved circuits, optimized for the latency and area, can increase the throughput of a manually designed classifier of application protocols. The classifier is intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array (FPGA). The classification is performed using the first packet carrying the application payload. The improvements in latency (and area) obtained by Cartesian genetic programming are validated using a professional FPGA design tool. The quality of classification is evaluated by means of real network data. All results are compared with commonly used classifiers based on regular expressions describing application protocols.

Klíčová slova

Application protocol, Classifier, Cartesian genetic programming, Field programmable gate array

Klíčová slova v angličtině

Application protocol, Classifier, Cartesian genetic programming, Field programmable gate array

Autoři

GROCHOL, D.; SEKANINA, L.; KOŘENEK, J.; ŽÁDNÍK, M.; KOŠAŘ, V.

Rok RIV

2017

Vydáno

01.01.2016

ISSN

1568-4946

Periodikum

APPLIED SOFT COMPUTING

Svazek

38

Číslo

1

Stát

Nizozemsko

Strany od

933

Strany do

941

Strany počet

9

URL

https://www.fit.vut.cz/research/publication/10900/

BibTex

@article{BUT130909,
  author="David {Grochol} and Lukáš {Sekanina} and Jan {Kořenek} and Martin {Žádník} and Vlastimil {Košař}",
  title="Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols",
  journal="APPLIED SOFT COMPUTING",
  year="2016",
  volume="38",
  number="1",
  pages="933--941",
  doi="10.1016/j.asoc.2015.09.046",
  issn="1568-4946",
  url="https://www.fit.vut.cz/research/publication/10900/"
}

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