Description in English
The goal of the research activities is to develop and implement testability analysis methodology such that the concepts and algorithms could be used in any design environment, to offer an alternative to the full scan approach. It is supposed that the structure of the circuit under analysis will be transformed into a database representing the diagnostic features of the circuit. The applicability will be verified on circuits described in VHDL language and on ISCAS benchmark circuits.

Keywords
diagnostika číslicových obvodů-analýya testovatelnosti

GA102/98/1463

Czech

Kotásek Zdeněk, doc. Ing., CSc. - principal person responsible

Department of Computer Systems
- responsible department (23.10.2001 - not assigned)
Faculty of Information Technology
- co-beneficiary (23.10.2001 - 31.3.2006)
Faculty of Information Technology
- beneficiary (1.1.1998 - 31.12.2000)

DRÁBEK, V. The Economic Analysis of Design for Testability. I&IT'99, Sci. Conf. Banska Bystrica, Slovakia. Banska Bystrica: unknown, 1999. p. 10-12.
Detail

DRÁBEK, V. The Unified Approach to Processor Testing. CE&I, Sci. Conf., Košice-Herlany, Slovakia. Košice-Herlany: unknown, 1999. p. 192-195. ISBN: 80-88922-05-4.
Detail

KOTÁSEK, Z.; ZBOŘIL, F. Boundary Scan of PCBs with Xilinx FPGAs. Sborník konference ECI98. Herlany: unknown, 1998. p. 70-74. ISBN: 80-88786-94-0.
Detail

KOTÁSEK, Z. Partial Scan Methodologies - a Survey. sborník konference The Eighth International Colloquium on Numerical Analysis and Computer Science with Applications. Plovdiv: unknown, 1999. p. 0-0.
Detail

KOTÁSEK, Z.; RŮŽIČKA, R. Behavioral Analysis for Testability on VHDL Source File. Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshopsborník konference IEEE DDECS. Bratislava: Slovak Academy of Science, 2000. p. 209-212. ISBN: 80-968320-3.
Detail

KOTÁSEK, Z.; RŮŽIČKA, R.; HLAVIČKA, J. Formal Approach to RTL Testability Analysis. sborník konference IEEE LATW 2000. Rio de Janeiro: unknown, 2000. p. 98-103.
Detail

KOTÁSEK, Z.; RŮŽIČKA, R. Partial Scan Methodologies - a Survey. sborník konference PDS2000. Ostrava: Elsevier Science, 2000. p. 133-137. ISBN: 0-08-043620-X.
Detail

RŮŽIČKA, R. Data Dependent I Path and their Utilisation in DFT. Sborník prací studentů a doktorandů FEI VUT. Brno: Akademické nakladatelství CERM, 2000. p. 228-230. ISBN: 80-7204-155-X.
Detail

KOTÁSEK, Z.; RŮŽIČKA, R. The Implementation of RTL Testability Analysis Algorithms trough the Discrete Mathematics Concepts. Proc. of the Fourth International Scientific Conference on Electronic Computers and Informatics. Košice-Herľany: unknown, 2000. p. 177-182. ISBN: 80-88922-25-9.
Detail

KOTÁSEK, Z.; RŮŽIČKA, R. Testability Analysis Based on Discrete Mathematics Concepts. Proc. of the 9-th International Colloquium on Numerical Analysis and Computer Science with Applications. Plovdiv: unknown, 2000. p. 0-0.
Detail

SLLAME, A.; SEKANINA, L. Simulation and Modeling of Evolvable Hardware Based Systems. MS2000 International Conference on Modeling and Simulation. Las Palmas de Gran Canaria: unknown, 2000. p. 485-492. ISBN: 84-95286-59-9.
Detail

KOTÁSEK, Z.; TOMÍŠEK, P.; ZBOŘIL, F. Testing PCBs Based on Boundary Scan and EDIF Data Analysis. Proceedings of the DDECS'98. Szczyrk: unknown, 1998. p. 95-101. ISBN: 83-908409-6-0.
Detail

KOTÁSEK, Z.; ZBOŘIL, F. Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory. Proceedings of the ECI'98. Herlany: Slovak Academy of Science, 1998. p. 75-80. ISBN: 80-88786-94-0.
Detail

KOTÁSEK, Z.; RŮŽIČKA, R.; ZBOŘIL, F. Partial Scan Methodology in VHDL Environment. CEI'99. Herľany: unknown, 1999. p. 146-151. ISBN: 80-88922-05-4.
Detail

KOTÁSEK, Z.; ZBOŘIL, F.; HLAVIČKA, J. Partial Scan Methodology for RTL Designs. Compendium of Papers ETW'99. Constance: unknown, 1999. p. 0-0. ISBN: 0-7695-0390-X.
Detail

ZBOŘIL, F., KOTÁSEK, Z. Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory. In Proceedings of the ECI'98. Herlany, SR: SAV, 1998. p. 75-80. ISBN: 80-88786-94-0.
Detail

SEKANINA, L.; RŮŽIČKA, R. Design of the Special Fast Reconfigurable Chip Using Common FPGA. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 161-168. ISBN: 80-968320-3-4.
Detail

SEKANINA, L.; DRÁBEK, V. Relation Between Fault Tolerance and Reconfiguration in Cellular Systems. 6th IEEE Int. On-Line Testing Workshop. Palma de Mallorca, Spain: IEEE Computer Society Press, 2000. p. 25-30. ISBN: 0-7695-0646-1.
Detail

SEKANINA, L.; DRÁBEK, V. Fault Tolerance and Reconfiguration in Cellular Systems. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 134-137. ISBN: 80-968320-3-4.
Detail

ZBOŘIL, F. VHDL RT Level Parser/Analyser of a Source Code. Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2000. p. 150-155. ISBN: 80-88922-25-9.
Detail

Responsibility: Kotásek Zdeněk, doc. Ing., CSc.