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KOTÁSEK, Z.; RŮŽIČKA, R.; HLAVIČKA, J.
Original Title
Formal Approach to RTL Testability Analysis
English Title
Type
Paper in proceedings outside WoS and Scopus
Original Abstract
In the paper a formal approach to the RT level testability analysis ispresented. It is based on the structural analysis of the circuit underdesign and the classification of circuit elements. The elements areclassified on the basis of their possible role during the testapplication. The principles known from the theory of sets andmathematical logic are utilised to define the role of registers duringthe test application. The principles of developing the RT leveltestability analysis algorithms are then presented to identifyregisters for partial scan and parallel paths to apply the test of thecircuit.
English abstract
Keywords
RTL testability analysis
Key words in English
Authors
Released
01.01.2000
Publisher
unknown
Location
Rio de Janeiro
Book
sborník konference IEEE LATW 2000
Pages from
98
Pages to
103
Pages count
6
BibTex
@inproceedings{BUT191916, author="Zdeněk {Kotásek} and Richard {Růžička} and Jan {Hlavička}", title="Formal Approach to RTL Testability Analysis", booktitle="sborník konference IEEE LATW 2000", year="2000", pages="98--103", publisher="unknown", address="Rio de Janeiro" }